diff mbox series

[U-Boot,2/3] ARM: socfpga: Init missing security policies on A10

Message ID 20180714115552.7114-2-marex@denx.de
State Accepted
Commit 42f4b83b52735d698bf3f3de2665bf6d42db9f1c
Delegated to: Marek Vasut
Headers show
Series [U-Boot,1/3] ARM: socfpga: Assure correct CPACR configuration | expand

Commit Message

Marek Vasut July 14, 2018, 11:55 a.m. UTC
The Arria10 requires proper configuration of the NOC firewall, otherwise
the access to certain areas of the LWHPS bridge fails in Linux. Add the
missing setup.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
---
 arch/arm/mach-socfpga/misc_arria10.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index a75cbc4ce6..80bf2f036f 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -93,6 +93,19 @@  static void initialize_security_policies(void)
 	/* Put OCRAM in non-secure */
 	writel(0x003f0000, &noc_fw_ocram_base->region0);
 	writel(0x1, &noc_fw_ocram_base->enable);
+
+	/* Put DDR in non-secure */
+	writel(0xffff0000, SOCFPGA_SDR_FIREWALL_L3_ADDRESS + 0xc);
+	writel(0x1, SOCFPGA_SDR_FIREWALL_L3_ADDRESS);
+
+	/* Enable priviledged and non-priviledged access to L4 peripherals */
+	writel(~0, SOCFPGA_NOC_L4_PRIV_FLT_OFST);
+
+	/* Enable secure and non-secure transactions to bridges */
+	writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST);
+	writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4);
+
+	writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set);
 }
 
 int arch_early_init_r(void)