diff mbox series

[PULL,13/28] mos6522: only clear the shift register interrupt upon write

Message ID 20180618035324.19907-14-david@gibson.dropbear.id.au
State New
Headers show
Series [PULL,01/28] target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache | expand

Commit Message

David Gibson June 18, 2018, 3:53 a.m. UTC 
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>

According to the 6522 datasheet the shift register (SR) interrupt flag is
cleared upon write with no mention of any other interrupt flags.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 hw/misc/mos6522.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 44eb306cf1..ad5041d8c0 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc/mos6522.c
@@ -241,7 +241,7 @@  uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
         break;
     case VIA_REG_SR:
         val = s->sr;
-        s->ifr &= ~(SR_INT | CB1_INT | CB2_INT);
+        s->ifr &= ~SR_INT;
         mos6522_update_irq(s);
         break;
     case VIA_REG_ACR: