| Message ID | 20180602141446.29982-2-stefanha@redhat.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm: add skeleton Cortex M0 CPU model | expand |
On 2 June 2018 at 15:14, Stefan Hajnoczi <stefanha@redhat.com> wrote: > Define a "cortex-m0" ARMv6-M CPU model. > > Most of the register reset values set by other CPU models are not > relevant for the cut-down ARMv6-M architecture. > > Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> > --- > target/arm/cpu.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 5d60893a07..aac224d809 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1215,6 +1215,16 @@ static void arm11mpcore_initfn(Object *obj) > cpu->reset_auxcr = 1; > } > > +static void cortex_m0_initfn(Object *obj) > +{ > + ARMCPU *cpu = ARM_CPU(obj); > + set_feature(&cpu->env, ARM_FEATURE_V6); > + set_feature(&cpu->env, ARM_FEATURE_M); > + > + /* TODO ARMv6-M doesn't support coprocessors, so how is this value accessed? */ > + cpu->midr = 0x410cc200; The MIDR is a memory-mapped register on M-profile (at 0xed00ed00); we implement this in hw/intc/armv7m_nvic.c. > +} > + > static void cortex_m3_initfn(Object *obj) > { > ARMCPU *cpu = ARM_CPU(obj); > @@ -1796,6 +1806,8 @@ static const ARMCPUInfo arm_cpus[] = { > { .name = "arm1136", .initfn = arm1136_initfn }, > { .name = "arm1176", .initfn = arm1176_initfn }, > { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, > + { .name = "cortex-m0", .initfn = cortex_m0_initfn, > + .class_init = arm_v7m_class_init /* TODO rename? */ }, We use v7m for a lot of stuff that's really M-profile in general (eg the v8m cortex-m33), so I wouldn't worry too much about renaming the function. thanks -- PMM
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5d60893a07..aac224d809 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1215,6 +1215,16 @@ static void arm11mpcore_initfn(Object *obj) cpu->reset_auxcr = 1; } +static void cortex_m0_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V6); + set_feature(&cpu->env, ARM_FEATURE_M); + + /* TODO ARMv6-M doesn't support coprocessors, so how is this value accessed? */ + cpu->midr = 0x410cc200; +} + static void cortex_m3_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -1796,6 +1806,8 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "arm1136", .initfn = arm1136_initfn }, { .name = "arm1176", .initfn = arm1176_initfn }, { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, + { .name = "cortex-m0", .initfn = cortex_m0_initfn, + .class_init = arm_v7m_class_init /* TODO rename? */ }, { .name = "cortex-m3", .initfn = cortex_m3_initfn, .class_init = arm_v7m_class_init }, { .name = "cortex-m4", .initfn = cortex_m4_initfn,
Define a "cortex-m0" ARMv6-M CPU model. Most of the register reset values set by other CPU models are not relevant for the cut-down ARMv6-M architecture. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> --- target/arm/cpu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)