| Message ID | 1303232375-25014-2-git-send-email-meador_inge@mentor.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Benjamin Herrenschmidt |
| Headers | show |
On Tue, 19 Apr 2011 11:59:34 -0500 Meador Inge <meador_inge@mentor.com> wrote: > + - interrupt-parent: Specifies the interrupt parent of the message register > + block. The type shall be a <phandle> and the value of that <phandle> > + shall point to the interrupt parent. interrupt-parent is not required; it can be inherited from an ancestor. In any case, this description doesn't say anything specifically about MPIC message nodes. > The default value shall be > + all a string of consecutive ones where the length of the run is equal > + to the number of registers in the block. For example, a block with > + four registers shall default to 0xF. Could be more simply worded as, "If not present, all message registers in the group are available." > +Required alias: > + > + In order for a message register block to be discovered it *must* define > + an alias in the 'aliases' node. I think the "in order to be discovered" statement is specific to your use case. > Aliases are of the form 'msgr-block<n>', > + where <n> is an integer specifying the block's number. Numbers shall start > + at 0. The hw docs refer to "group A" and "group B", not "block 0" and "block 1". Plus, I'd put "mpic-" in the alias name. > +Example: > + > + /* The aliases needed to define an order on the message register blocks. > + */ > + aliases { > + msgr-block0 = &msgr_block0; > + msgr-block1 = &msgr_block1; > + }; > + > + msgr_block0: msgr-block@41400 { > + compatible = "fsl,mpic-v3.1-msgr"; > + reg = <0x41400 0x200>; > + // Message registers 0 and 3 in this block can receive interrupts on > + // sources 0xb0 and 0xb2, respectively. > + interrupts = <0xb0 2 0xb2 2>; > + msg-receive-mask = <0x5>; > + interrupt-parent = <&mpic>; > + }; A mask of 0x5 specifies message registers 0 and 2 (as do interrupts 0xb0 and 0xb2), not 0 and 3. -Scott
On 04/19/2011 12:52 PM, Scott Wood wrote: > On Tue, 19 Apr 2011 11:59:34 -0500 > Meador Inge <meador_inge@mentor.com> wrote: > >> + - interrupt-parent: Specifies the interrupt parent of the message register >> + block. The type shall be a <phandle> and the value of that <phandle> >> + shall point to the interrupt parent. > > interrupt-parent is not required; it can be inherited from an ancestor. In > any case, this description doesn't say anything specifically about MPIC > message nodes. Removed. >> The default value shall be >> + all a string of consecutive ones where the length of the run is equal >> + to the number of registers in the block. For example, a block with >> + four registers shall default to 0xF. > > Could be more simply worded as, "If not present, all message registers in > the group are available." That is much better. >> +Required alias: >> + >> + In order for a message register block to be discovered it *must* define >> + an alias in the 'aliases' node. > > I think the "in order to be discovered" statement is specific to your use > case. > >> Aliases are of the form 'msgr-block<n>', >> + where <n> is an integer specifying the block's number. Numbers shall start >> + at 0. > > The hw docs refer to "group A" and "group B", not "block 0" and "block 1". > > Plus, I'd put "mpic-" in the alias name. Are you suggesting that the alias should be called: 'mpic-groupA', 'mpic-groupB', 'mpic-groupC', etc... ? Or just that I should use the terminology group instead of block where discussing things in the binding? >> +Example: >> + >> + /* The aliases needed to define an order on the message register blocks. >> + */ >> + aliases { >> + msgr-block0 = &msgr_block0; >> + msgr-block1 = &msgr_block1; >> + }; >> + >> + msgr_block0: msgr-block@41400 { >> + compatible = "fsl,mpic-v3.1-msgr"; >> + reg = <0x41400 0x200>; >> + // Message registers 0 and 3 in this block can receive interrupts on >> + // sources 0xb0 and 0xb2, respectively. >> + interrupts = <0xb0 2 0xb2 2>; >> + msg-receive-mask = <0x5>; >> + interrupt-parent = <&mpic>; >> + }; > > A mask of 0x5 specifies message registers 0 and 2 (as do interrupts 0xb0 > and 0xb2), not 0 and 3. > Fixed. Thanks.
On Tue, 19 Apr 2011 13:26:26 -0500 Meador Inge <meador_inge@mentor.com> wrote: > On 04/19/2011 12:52 PM, Scott Wood wrote: > > On Tue, 19 Apr 2011 11:59:34 -0500 > > Meador Inge <meador_inge@mentor.com> wrote: > > > >> Aliases are of the form 'msgr-block<n>', > >> + where <n> is an integer specifying the block's number. Numbers shall start > >> + at 0. > > > > The hw docs refer to "group A" and "group B", not "block 0" and "block 1". > > > > Plus, I'd put "mpic-" in the alias name. > > Are you suggesting that the alias should be called: 'mpic-groupA', > 'mpic-groupB', 'mpic-groupC', etc... ? I was thinking something like "mpic-msgr-group-a", "mpic-msgr-group-b" -- though if you want to use numbers instead to more easily map to potential APIs, that's OK. -Scott
On 04/19/2011 01:33 PM, Scott Wood wrote: > On Tue, 19 Apr 2011 13:26:26 -0500 > Meador Inge <meador_inge@mentor.com> wrote: > >> On 04/19/2011 12:52 PM, Scott Wood wrote: >>> On Tue, 19 Apr 2011 11:59:34 -0500 >>> Meador Inge <meador_inge@mentor.com> wrote: >>> >>>> Aliases are of the form 'msgr-block<n>', >>>> + where <n> is an integer specifying the block's number. Numbers shall start >>>> + at 0. >>> >>> The hw docs refer to "group A" and "group B", not "block 0" and "block 1". >>> >>> Plus, I'd put "mpic-" in the alias name. >> >> Are you suggesting that the alias should be called: 'mpic-groupA', >> 'mpic-groupB', 'mpic-groupC', etc... ? > > I was thinking something like "mpic-msgr-group-a", "mpic-msgr-group-b" -- > though if you want to use numbers instead to more easily map to potential > APIs, that's OK. > Hmmm ... In the MPC8572E and P1022DS manuals I don't see the terminology group used for message registers. The MPIC global timers on the other hand do use group A and group B. I will definitely add the 'mpic-' prefix, but unless I am looking in the wrong place in the manuals, then I am not so sure there are MPIC message register groups. As a side note, the term "register block" pops up in a few places not related to message registers. If you feel like group is a more idiomatic term, I can change it.
On Thu, 21 Apr 2011 14:26:46 -0500 Meador Inge <meador_inge@mentor.com> wrote: > Hmmm ... In the MPC8572E and P1022DS manuals I don't see the terminology > group used for message registers. I was looking at the P4080 manual, which does use it. It looks like some other chip manuals just use MSGR0-MSGR7. > If you feel like group is a more idiomatic term, I can change it. Since the docs aren't consistent, I don't really have a strong opinion here. Just make clear in the binding what you're referring to. -Scott
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt new file mode 100644 index 0000000..41f1965 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt @@ -0,0 +1,71 @@ +* FSL MPIC Message Registers + +This binding specifies what properties must be available in the device tree +representation of the message register blocks found in some FSL MPIC +implementations. + +Required properties: + + - compatible: Specifies the compatibility list for the message register + block. The type shall be <string> and the value shall be of the form + "fsl,mpic-v<version>-msgr", where <version> is the version number of + the MPIC containing the message registers. + + - reg: Specifies the base physical address(s) and size(s) of the + message register block's addressable register space. The type shall be + <prop-encoded-array>. + + - interrupts: Specifies a list of interrupt source and level-sense pairs. + The type shall be <prop-encoded-array>. The length shall be equal to + the number of bits set in the 'msg-receive-mask' property value. + + - interrupt-parent: Specifies the interrupt parent of the message register + block. The type shall be a <phandle> and the value of that <phandle> + shall point to the interrupt parent. + +Optional properties: + + - msg-receive-mask: Specifies what registers in the containing block are + allowed to receive interrupts. The value is a bit mask where a set bit + at bit 'n' indicates that message register 'n' can receive interrupts. + The type shall be <prop-encoded-array>. The default value shall be + all a string of consecutive ones where the length of the run is equal + to the number of registers in the block. For example, a block with + four registers shall default to 0xF. + +Required alias: + + In order for a message register block to be discovered it *must* define + an alias in the 'aliases' node. Aliases are of the form 'msgr-block<n>', + where <n> is an integer specifying the block's number. Numbers shall start + at 0. + +Example: + + /* The aliases needed to define an order on the message register blocks. + */ + aliases { + msgr-block0 = &msgr_block0; + msgr-block1 = &msgr_block1; + }; + + msgr_block0: msgr-block@41400 { + compatible = "fsl,mpic-v3.1-msgr"; + reg = <0x41400 0x200>; + // Message registers 0 and 3 in this block can receive interrupts on + // sources 0xb0 and 0xb2, respectively. + interrupts = <0xb0 2 0xb2 2>; + msg-receive-mask = <0x5>; + interrupt-parent = <&mpic>; + }; + + msgr_block1: msgr-block@42400 { + compatible = "fsl,mpic-v3.1-msgr"; + reg = <0x42400 0x200>; + // Message registers 0 and 3 in this block can receive interrupts on + // sources 0xb4 and 0xb6, respectively. + interrupts = <0xb4 2 0xb6 2>; + msg-receive-mask = <0x5>; + interrupt-parent = <&mpic>; + }; +
This binding documents how the message register blocks found in some FSL MPIC implementations shall be represented in a device tree. Signed-off-by: Meador Inge <meador_inge@mentor.com> Cc: Hollis Blanchard <hollis_blanchard@mentor.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> --- .../devicetree/bindings/powerpc/fsl/mpic-msgr.txt | 71 ++++++++++++++++++++ 1 files changed, 71 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt