diff mbox series

igb: Clear TSICR interrupts together with ICR

Message ID dc3f47f4-22b2-87d7-3959-9da530efbfe3@trackman.com
State Accepted
Delegated to: Jeff Kirsher
Headers show
Series igb: Clear TSICR interrupts together with ICR | expand

Commit Message

Joanna Yurdal May 16, 2018, 11:14 a.m. UTC
I have been working with the PTP using IGB i210 and the linux driver
can end up in a state where it stops receiving E1000_ICR_TS interrupt.
The ethernet driver works fine but PPS stops and no tx ptp timestamp
can be retrieved. This is caused by not clearing the TS interrupt before enabling igb interrupts in the igb_up function.

Comments

Brown, Aaron F May 26, 2018, 1:24 a.m. UTC | #1
> From: Intel-wired-lan [mailto:intel-wired-lan-bounces@osuosl.org] On
> Behalf Of Joanna Yurdal
> Sent: Wednesday, May 16, 2018 4:14 AM
> To: intel-wired-lan@lists.osuosl.org
> Subject: [Intel-wired-lan] [PATCH] igb: Clear TSICR interrupts together with
> ICR
> 
> I have been working with the PTP using IGB i210 and the linux driver
> can end up in a state where it stops receiving E1000_ICR_TS interrupt.
> The ethernet driver works fine but PPS stops and no tx ptp timestamp
> can be retrieved. This is caused by not clearing the TS interrupt before
> enabling igb interrupts in the igb_up function.

Tested-by: Aaron Brown <aaron.f.brown@intel.com>
diff mbox series

Patch

From 8e3eeef09b9960c67917a7f7fafe47751c0932fe Mon Sep 17 00:00:00 2001
From: Joanna Yurdal <jyu@trackman.com>
Date: Tue, 15 May 2018 12:55:10 +0200
Subject: [PATCH] igb: Clear TSICR interrupts together with ICR

Issuing "ip link set up/down" can block TSICR interrupts, what results in
missing PTP tx timestamp and no PPS pulse generation.

Problem happens when the link is set up with the TSICR interrupts pending.
ICR is cleared before enabling interrupts, while TSICR is not. When all TSICR
interrupts are pending at this moment, time_sync interrupt will never
be generated. TSICR should be cleared as well.

In order to reproduce the issue:
1. Setup linux with IEEE 1588 grandmaster and PPS output enabled
2. Continue setting link up/down with random intervals between commands
3. Wait until PPS is not generated ( only one pulse is generated and PPS
dies), and ptp4l complains constantly about tx timeout.

Signed-off-by: Joanna Yurdal <jyu@trackman.com>
---
 drivers/net/ethernet/intel/igb/igb_main.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c
index c1c0bc3..5350644 100644
--- a/drivers/net/ethernet/intel/igb/igb_main.c
+++ b/drivers/net/ethernet/intel/igb/igb_main.c
@@ -2063,6 +2063,7 @@  int igb_up(struct igb_adapter *adapter)
 		igb_assign_vector(adapter->q_vector[0], 0);
 
 	/* Clear any pending interrupts. */
+	rd32(E1000_TSICR);
 	rd32(E1000_ICR);
 	igb_irq_enable(adapter);
 
@@ -3621,6 +3622,7 @@  static int __igb_open(struct net_device *netdev, bool resuming)
 		napi_enable(&(adapter->q_vector[i]->napi));
 
 	/* Clear any pending interrupts. */
+	rd32(E1000_TSICR);
 	rd32(E1000_ICR);
 
 	igb_irq_enable(adapter);
-- 
2.7.4