diff mbox series

[U-Boot,v1,07/16] arm: socfpga: stratix10: Add misc support for Stratix10 SoC

Message ID 1524131457-19234-8-git-send-email-ley.foon.tan@intel.com
State Superseded
Delegated to: Marek Vasut
Headers show
Series Add Intel Stratix 10 SoC support | expand

Commit Message

Ley Foon Tan April 19, 2018, 9:50 a.m. UTC 
Add misc support such as EMAC and cpu info printout for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/Makefile   |    1 +
 arch/arm/mach-socfpga/misc_s10.c |  103 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 104 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/misc_s10.c

Comments

Marek Vasut April 19, 2018, 2:49 a.m. UTC | #1 
On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
> Add misc support such as EMAC and cpu info printout for Stratix SoC
> 
> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> ---
>  arch/arm/mach-socfpga/Makefile   |    1 +
>  arch/arm/mach-socfpga/misc_s10.c |  103 ++++++++++++++++++++++++++++++++++++++
>  2 files changed, 104 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/misc_s10.c
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index 910eb6f..b253914 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -32,6 +32,7 @@ endif
>  
>  ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>  obj-y	+= clock_manager_s10.o
> +obj-y	+= misc_s10.o
>  obj-y	+= reset_manager_s10.o
>  obj-y	+= system_manager_s10.o
>  obj-y	+= wrap_pinmux_config_s10.o
> diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
> new file mode 100644
> index 0000000..b1cc6ca
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/misc_s10.c
> @@ -0,0 +1,103 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
> + *
> + */
> +
> +#include <altera.h>
> +#include <common.h>
> +#include <errno.h>
> +#include <fdtdec.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <watchdog.h>
> +#include <asm/io.h>
> +#include <asm/arch/reset_manager.h>
> +#include <asm/arch/system_manager.h>
> +#include <asm/arch/misc.h>
> +#include <asm/pl310.h>
> +#include <linux/libfdt.h>
> +
> +#include <dt-bindings/reset/altr,rst-mgr-s10.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static struct socfpga_system_manager *sysmgr_regs =
> +	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> +
> +/*
> + * DesignWare Ethernet initialization
> + */
> +#ifdef CONFIG_ETH_DESIGNWARE

Use the reset framework ? Talk to Dinh if in doubt

> +void dwmac_deassert_reset(const unsigned int of_reset_id,
> +			  const u32 phymode)
> +{
> +	/* Put the emac we're using into reset.
> +	 * This is required before configuring the PHY interface
> +	 */
> +	socfpga_emac_manage_reset(of_reset_id, 1);
> +
> +	clrsetbits_le32(&sysmgr_regs->emac0 + (of_reset_id - EMAC0_RESET),
> +			SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
> +			phymode);
> +
> +	socfpga_emac_manage_reset(of_reset_id, 0);
> +}
> +#endif
> +
> +/*
> + * Print CPU information
> + */
> +#if defined(CONFIG_DISPLAY_CPUINFO)
> +int print_cpuinfo(void)
> +{
> +	puts("CPU:   Intel FPGA SoCFPGA Platform\n");
> +	puts("FPGA:  Intel FPGA Stratix 10\n");

This can well come from DT.

> +	return 0;
> +}
> +#endif
> +
> +#ifdef CONFIG_ARCH_MISC_INIT
> +int arch_misc_init(void)
> +{
> +	char qspi_string[13];
> +
> +	sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
> +	env_set("qspi_clock", qspi_string);
> +
> +	return socfpga_eth_reset();
> +}
> +#endif
> +
> +int arch_early_init_r(void)
> +{
> +	return 0;

Needed ?

> +}
> +
> +int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> +{
> +	if (argc != 2)
> +		return CMD_RET_USAGE;
> +
> +	argv++;
> +
> +	switch (*argv[0]) {
> +	case 'e':	/* Enable */
> +		socfpga_bridges_reset(1);
> +		break;
> +	case 'd':	/* Disable */
> +		socfpga_bridges_reset(0);
> +		break;

Do you really need to duplicate this command ?

> +	default:
> +		return CMD_RET_USAGE;
> +	}
> +
> +	return 0;
> +}
> +
> +U_BOOT_CMD(bridge, 2, 1, do_bridge,
> +	   "SoCFPGA HPS FPGA bridge control",
> +	   "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
> +	   "bridge disable - Disable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
> +	   ""
> +);
>
Ley Foon Tan April 27, 2018, 2:10 a.m. UTC | #2 
On Thu, Apr 19, 2018 at 10:49 AM, Marek Vasut <marex@denx.de> wrote:
> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>> Add misc support such as EMAC and cpu info printout for Stratix SoC
>>
>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>> ---
>>  arch/arm/mach-socfpga/Makefile   |    1 +
>>  arch/arm/mach-socfpga/misc_s10.c |  103 ++++++++++++++++++++++++++++++++++++++
>>  2 files changed, 104 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/mach-socfpga/misc_s10.c
>>
>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
>> index 910eb6f..b253914 100644
>> --- a/arch/arm/mach-socfpga/Makefile
>> +++ b/arch/arm/mach-socfpga/Makefile
>> @@ -32,6 +32,7 @@ endif
>>
>>  ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>>  obj-y        += clock_manager_s10.o
>> +obj-y        += misc_s10.o
>>  obj-y        += reset_manager_s10.o
>>  obj-y        += system_manager_s10.o
>>  obj-y        += wrap_pinmux_config_s10.o
>> diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
>> new file mode 100644
>> index 0000000..b1cc6ca
>> --- /dev/null
>> +++ b/arch/arm/mach-socfpga/misc_s10.c
>> @@ -0,0 +1,103 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
>> + *
>> + */
>> +
>> +#include <altera.h>
>> +#include <common.h>
>> +#include <errno.h>
>> +#include <fdtdec.h>
>> +#include <miiphy.h>
>> +#include <netdev.h>
>> +#include <watchdog.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/reset_manager.h>
>> +#include <asm/arch/system_manager.h>
>> +#include <asm/arch/misc.h>
>> +#include <asm/pl310.h>
>> +#include <linux/libfdt.h>
>> +
>> +#include <dt-bindings/reset/altr,rst-mgr-s10.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static struct socfpga_system_manager *sysmgr_regs =
>> +     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>> +
>> +/*
>> + * DesignWare Ethernet initialization
>> + */
>> +#ifdef CONFIG_ETH_DESIGNWARE
>
> Use the reset framework ? Talk to Dinh if in doubt
Yes, will convert this to reset framework. Will send out separate
patches to convert device drivers to use reset framework.

>
>> +void dwmac_deassert_reset(const unsigned int of_reset_id,
>> +                       const u32 phymode)
>> +{
>> +     /* Put the emac we're using into reset.
>> +      * This is required before configuring the PHY interface
>> +      */
>> +     socfpga_emac_manage_reset(of_reset_id, 1);
>> +
>> +     clrsetbits_le32(&sysmgr_regs->emac0 + (of_reset_id - EMAC0_RESET),
>> +                     SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
>> +                     phymode);
>> +
>> +     socfpga_emac_manage_reset(of_reset_id, 0);
>> +}
>> +#endif
>> +
>> +/*
>> + * Print CPU information
>> + */
>> +#if defined(CONFIG_DISPLAY_CPUINFO)
>> +int print_cpuinfo(void)
>> +{
>> +     puts("CPU:   Intel FPGA SoCFPGA Platform\n");
>> +     puts("FPGA:  Intel FPGA Stratix 10\n");
>
> This can well come from DT.

DT only contains the "model" and this is already display in
common/board_info.c:show_board_info().
So, will use simple puts here for the CPU info, unless we want add new
DT property.

Below is example output from console, model is retrieved from DT.

CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Stratix 10 SoCDK


>
>> +     return 0;
>> +}
>> +#endif
>> +
>> +#ifdef CONFIG_ARCH_MISC_INIT
>> +int arch_misc_init(void)
>> +{
>> +     char qspi_string[13];
>> +
>> +     sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
>> +     env_set("qspi_clock", qspi_string);
>> +
>> +     return socfpga_eth_reset();
>> +}
>> +#endif
>> +
>> +int arch_early_init_r(void)
>> +{
>> +     return 0;
>
> Needed ?
Will remove.
>
>> +}
>> +
>> +int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>> +{
>> +     if (argc != 2)
>> +             return CMD_RET_USAGE;
>> +
>> +     argv++;
>> +
>> +     switch (*argv[0]) {
>> +     case 'e':       /* Enable */
>> +             socfpga_bridges_reset(1);
>> +             break;
>> +     case 'd':       /* Disable */
>> +             socfpga_bridges_reset(0);
>> +             break;
>
> Do you really need to duplicate this command ?
Will rework this part and merge with Gen5.
>
>> +     default:
>> +             return CMD_RET_USAGE;
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>> +U_BOOT_CMD(bridge, 2, 1, do_bridge,
>> +        "SoCFPGA HPS FPGA bridge control",
>> +        "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
>> +        "bridge disable - Disable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
>> +        ""
>> +);
>>

Thanks.

Regards
Ley Foon
Marek Vasut April 27, 2018, 7:05 a.m. UTC | #3 
On 04/27/2018 04:10 AM, Ley Foon Tan wrote:
> On Thu, Apr 19, 2018 at 10:49 AM, Marek Vasut <marex@denx.de> wrote:
>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>> Add misc support such as EMAC and cpu info printout for Stratix SoC
>>>
>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>> ---
>>>  arch/arm/mach-socfpga/Makefile   |    1 +
>>>  arch/arm/mach-socfpga/misc_s10.c |  103 ++++++++++++++++++++++++++++++++++++++
>>>  2 files changed, 104 insertions(+), 0 deletions(-)
>>>  create mode 100644 arch/arm/mach-socfpga/misc_s10.c
>>>
>>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
>>> index 910eb6f..b253914 100644
>>> --- a/arch/arm/mach-socfpga/Makefile
>>> +++ b/arch/arm/mach-socfpga/Makefile
>>> @@ -32,6 +32,7 @@ endif
>>>
>>>  ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>>>  obj-y        += clock_manager_s10.o
>>> +obj-y        += misc_s10.o
>>>  obj-y        += reset_manager_s10.o
>>>  obj-y        += system_manager_s10.o
>>>  obj-y        += wrap_pinmux_config_s10.o
>>> diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
>>> new file mode 100644
>>> index 0000000..b1cc6ca
>>> --- /dev/null
>>> +++ b/arch/arm/mach-socfpga/misc_s10.c
>>> @@ -0,0 +1,103 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
>>> + *
>>> + */
>>> +
>>> +#include <altera.h>
>>> +#include <common.h>
>>> +#include <errno.h>
>>> +#include <fdtdec.h>
>>> +#include <miiphy.h>
>>> +#include <netdev.h>
>>> +#include <watchdog.h>
>>> +#include <asm/io.h>
>>> +#include <asm/arch/reset_manager.h>
>>> +#include <asm/arch/system_manager.h>
>>> +#include <asm/arch/misc.h>
>>> +#include <asm/pl310.h>
>>> +#include <linux/libfdt.h>
>>> +
>>> +#include <dt-bindings/reset/altr,rst-mgr-s10.h>
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +static struct socfpga_system_manager *sysmgr_regs =
>>> +     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>>> +
>>> +/*
>>> + * DesignWare Ethernet initialization
>>> + */
>>> +#ifdef CONFIG_ETH_DESIGNWARE
>>
>> Use the reset framework ? Talk to Dinh if in doubt
> Yes, will convert this to reset framework. Will send out separate
> patches to convert device drivers to use reset framework.

Thanks, this really helps even for the A10.

http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/arria10

>>> +void dwmac_deassert_reset(const unsigned int of_reset_id,
>>> +                       const u32 phymode)
>>> +{
>>> +     /* Put the emac we're using into reset.
>>> +      * This is required before configuring the PHY interface
>>> +      */
>>> +     socfpga_emac_manage_reset(of_reset_id, 1);
>>> +
>>> +     clrsetbits_le32(&sysmgr_regs->emac0 + (of_reset_id - EMAC0_RESET),
>>> +                     SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
>>> +                     phymode);
>>> +
>>> +     socfpga_emac_manage_reset(of_reset_id, 0);
>>> +}
>>> +#endif
>>> +
>>> +/*
>>> + * Print CPU information
>>> + */
>>> +#if defined(CONFIG_DISPLAY_CPUINFO)
>>> +int print_cpuinfo(void)
>>> +{
>>> +     puts("CPU:   Intel FPGA SoCFPGA Platform\n");
>>> +     puts("FPGA:  Intel FPGA Stratix 10\n");
>>
>> This can well come from DT.
> 
> DT only contains the "model" and this is already display in
> common/board_info.c:show_board_info().
> So, will use simple puts here for the CPU info, unless we want add new
> DT property.

I don't, nope.

> Below is example output from console, model is retrieved from DT.
> 
> CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
> Model: SoCFPGA Stratix 10 SoCDK

Ah OK, got it.

>>> +     return 0;
>>> +}
>>> +#endif
>>> +
>>> +#ifdef CONFIG_ARCH_MISC_INIT
>>> +int arch_misc_init(void)
>>> +{
>>> +     char qspi_string[13];
>>> +
>>> +     sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
>>> +     env_set("qspi_clock", qspi_string);
>>> +
>>> +     return socfpga_eth_reset();
>>> +}
>>> +#endif
>>> +
>>> +int arch_early_init_r(void)
>>> +{
>>> +     return 0;
>>
>> Needed ?
> Will remove.
>>
>>> +}
>>> +
>>> +int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>>> +{
>>> +     if (argc != 2)
>>> +             return CMD_RET_USAGE;
>>> +
>>> +     argv++;
>>> +
>>> +     switch (*argv[0]) {
>>> +     case 'e':       /* Enable */
>>> +             socfpga_bridges_reset(1);
>>> +             break;
>>> +     case 'd':       /* Disable */
>>> +             socfpga_bridges_reset(0);
>>> +             break;
>>
>> Do you really need to duplicate this command ?
> Will rework this part and merge with Gen5.

Great!

>>
>>> +     default:
>>> +             return CMD_RET_USAGE;
>>> +     }
>>> +
>>> +     return 0;
>>> +}
>>> +
>>> +U_BOOT_CMD(bridge, 2, 1, do_bridge,
>>> +        "SoCFPGA HPS FPGA bridge control",
>>> +        "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
>>> +        "bridge disable - Disable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
>>> +        ""
>>> +);
>>>
> 
> Thanks.
> 
> Regards
> Ley Foon
>
Ley Foon Tan April 27, 2018, 8:04 a.m. UTC | #4 
On Fri, Apr 27, 2018 at 3:05 PM, Marek Vasut <marex@denx.de> wrote:
> On 04/27/2018 04:10 AM, Ley Foon Tan wrote:
>> On Thu, Apr 19, 2018 at 10:49 AM, Marek Vasut <marex@denx.de> wrote:
>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>> Add misc support such as EMAC and cpu info printout for Stratix SoC
>>>>
>>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>>> ---
>>>>  arch/arm/mach-socfpga/Makefile   |    1 +
>>>>  arch/arm/mach-socfpga/misc_s10.c |  103 ++++++++++++++++++++++++++++++++++++++
>>>>  2 files changed, 104 insertions(+), 0 deletions(-)
>>>>  create mode 100644 arch/arm/mach-socfpga/misc_s10.c
>>>>
>>>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
>>>> index 910eb6f..b253914 100644
>>>> --- a/arch/arm/mach-socfpga/Makefile
>>>> +++ b/arch/arm/mach-socfpga/Makefile
>>>> @@ -32,6 +32,7 @@ endif
>>>>
>>>>  ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>>>>  obj-y        += clock_manager_s10.o
>>>> +obj-y        += misc_s10.o
>>>>  obj-y        += reset_manager_s10.o
>>>>  obj-y        += system_manager_s10.o
>>>>  obj-y        += wrap_pinmux_config_s10.o
>>>> diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
>>>> new file mode 100644
>>>> index 0000000..b1cc6ca
>>>> --- /dev/null
>>>> +++ b/arch/arm/mach-socfpga/misc_s10.c
>>>> @@ -0,0 +1,103 @@
>>>> +// SPDX-License-Identifier: GPL-2.0
>>>> +/*
>>>> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
>>>> + *
>>>> + */
>>>> +
>>>> +#include <altera.h>
>>>> +#include <common.h>
>>>> +#include <errno.h>
>>>> +#include <fdtdec.h>
>>>> +#include <miiphy.h>
>>>> +#include <netdev.h>
>>>> +#include <watchdog.h>
>>>> +#include <asm/io.h>
>>>> +#include <asm/arch/reset_manager.h>
>>>> +#include <asm/arch/system_manager.h>
>>>> +#include <asm/arch/misc.h>
>>>> +#include <asm/pl310.h>
>>>> +#include <linux/libfdt.h>
>>>> +
>>>> +#include <dt-bindings/reset/altr,rst-mgr-s10.h>
>>>> +
>>>> +DECLARE_GLOBAL_DATA_PTR;
>>>> +
>>>> +static struct socfpga_system_manager *sysmgr_regs =
>>>> +     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>>>> +
>>>> +/*
>>>> + * DesignWare Ethernet initialization
>>>> + */
>>>> +#ifdef CONFIG_ETH_DESIGNWARE
>>>
>>> Use the reset framework ? Talk to Dinh if in doubt
>> Yes, will convert this to reset framework. Will send out separate
>> patches to convert device drivers to use reset framework.
>
> Thanks, this really helps even for the A10.
>
> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/arria10

I saw you have new patches on this git repo, should I rebase my
patchset on top of this git repo or using main u-boot.git?

Regards
Ley Foon
Marek Vasut April 27, 2018, 8:30 a.m. UTC | #5 
On 04/27/2018 10:04 AM, Ley Foon Tan wrote:
> On Fri, Apr 27, 2018 at 3:05 PM, Marek Vasut <marex@denx.de> wrote:
>> On 04/27/2018 04:10 AM, Ley Foon Tan wrote:
>>> On Thu, Apr 19, 2018 at 10:49 AM, Marek Vasut <marex@denx.de> wrote:
>>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>>> Add misc support such as EMAC and cpu info printout for Stratix SoC
>>>>>
>>>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>>>> ---
>>>>>  arch/arm/mach-socfpga/Makefile   |    1 +
>>>>>  arch/arm/mach-socfpga/misc_s10.c |  103 ++++++++++++++++++++++++++++++++++++++
>>>>>  2 files changed, 104 insertions(+), 0 deletions(-)
>>>>>  create mode 100644 arch/arm/mach-socfpga/misc_s10.c
>>>>>
>>>>> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
>>>>> index 910eb6f..b253914 100644
>>>>> --- a/arch/arm/mach-socfpga/Makefile
>>>>> +++ b/arch/arm/mach-socfpga/Makefile
>>>>> @@ -32,6 +32,7 @@ endif
>>>>>
>>>>>  ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
>>>>>  obj-y        += clock_manager_s10.o
>>>>> +obj-y        += misc_s10.o
>>>>>  obj-y        += reset_manager_s10.o
>>>>>  obj-y        += system_manager_s10.o
>>>>>  obj-y        += wrap_pinmux_config_s10.o
>>>>> diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
>>>>> new file mode 100644
>>>>> index 0000000..b1cc6ca
>>>>> --- /dev/null
>>>>> +++ b/arch/arm/mach-socfpga/misc_s10.c
>>>>> @@ -0,0 +1,103 @@
>>>>> +// SPDX-License-Identifier: GPL-2.0
>>>>> +/*
>>>>> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
>>>>> + *
>>>>> + */
>>>>> +
>>>>> +#include <altera.h>
>>>>> +#include <common.h>
>>>>> +#include <errno.h>
>>>>> +#include <fdtdec.h>
>>>>> +#include <miiphy.h>
>>>>> +#include <netdev.h>
>>>>> +#include <watchdog.h>
>>>>> +#include <asm/io.h>
>>>>> +#include <asm/arch/reset_manager.h>
>>>>> +#include <asm/arch/system_manager.h>
>>>>> +#include <asm/arch/misc.h>
>>>>> +#include <asm/pl310.h>
>>>>> +#include <linux/libfdt.h>
>>>>> +
>>>>> +#include <dt-bindings/reset/altr,rst-mgr-s10.h>
>>>>> +
>>>>> +DECLARE_GLOBAL_DATA_PTR;
>>>>> +
>>>>> +static struct socfpga_system_manager *sysmgr_regs =
>>>>> +     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>>>>> +
>>>>> +/*
>>>>> + * DesignWare Ethernet initialization
>>>>> + */
>>>>> +#ifdef CONFIG_ETH_DESIGNWARE
>>>>
>>>> Use the reset framework ? Talk to Dinh if in doubt
>>> Yes, will convert this to reset framework. Will send out separate
>>> patches to convert device drivers to use reset framework.
>>
>> Thanks, this really helps even for the A10.
>>
>> http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/arria10
> 
> I saw you have new patches on this git repo, should I rebase my
> patchset on top of this git repo or using main u-boot.git?

Is there anything that'll collide ? If you find anything useful there,
feel free to use it.
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 910eb6f..b253914 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,6 +32,7 @@  endif
 
 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y	+= clock_manager_s10.o
+obj-y	+= misc_s10.o
 obj-y	+= reset_manager_s10.o
 obj-y	+= system_manager_s10.o
 obj-y	+= wrap_pinmux_config_s10.o
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
new file mode 100644
index 0000000..b1cc6ca
--- /dev/null
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -0,0 +1,103 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <altera.h>
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/misc.h>
+#include <asm/pl310.h>
+#include <linux/libfdt.h>
+
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_ETH_DESIGNWARE
+void dwmac_deassert_reset(const unsigned int of_reset_id,
+			  const u32 phymode)
+{
+	/* Put the emac we're using into reset.
+	 * This is required before configuring the PHY interface
+	 */
+	socfpga_emac_manage_reset(of_reset_id, 1);
+
+	clrsetbits_le32(&sysmgr_regs->emac0 + (of_reset_id - EMAC0_RESET),
+			SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+			phymode);
+
+	socfpga_emac_manage_reset(of_reset_id, 0);
+}
+#endif
+
+/*
+ * Print CPU information
+ */
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	puts("CPU:   Intel FPGA SoCFPGA Platform\n");
+	puts("FPGA:  Intel FPGA Stratix 10\n");
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+	char qspi_string[13];
+
+	sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
+	env_set("qspi_clock", qspi_string);
+
+	return socfpga_eth_reset();
+}
+#endif
+
+int arch_early_init_r(void)
+{
+	return 0;
+}
+
+int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc != 2)
+		return CMD_RET_USAGE;
+
+	argv++;
+
+	switch (*argv[0]) {
+	case 'e':	/* Enable */
+		socfpga_bridges_reset(1);
+		break;
+	case 'd':	/* Disable */
+		socfpga_bridges_reset(0);
+		break;
+	default:
+		return CMD_RET_USAGE;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(bridge, 2, 1, do_bridge,
+	   "SoCFPGA HPS FPGA bridge control",
+	   "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+	   "bridge disable - Disable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+	   ""
+);