| Message ID | 1524131457-19234-6-git-send-email-ley.foon.tan@intel.com |
|---|---|
| State | Superseded |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | Add Intel Stratix 10 SoC support | expand |
On 04/19/2018 11:50 AM, Ley Foon Tan wrote: > Add CONFIG_SYS_L2_PL310 conditional build. Why ? > Signed-off-by: Chin Liang See <chin.liang.see@intel.com> > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> > --- > arch/arm/mach-socfpga/misc.c | 4 ++++ > 1 files changed, 4 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c > index 692466c..01f824c 100644 > --- a/arch/arm/mach-socfpga/misc.c > +++ b/arch/arm/mach-socfpga/misc.c > @@ -23,8 +23,10 @@ > > DECLARE_GLOBAL_DATA_PTR; > > +#ifdef CONFIG_SYS_L2_PL310 > static const struct pl310_regs *const pl310 = > (struct pl310_regs *)CONFIG_SYS_PL310_BASE; > +#endif > > struct bsel bsel_str[] = { > { "rsvd", "Reserved", }, > @@ -53,6 +55,7 @@ void enable_caches(void) > #endif > } > > +#ifdef CONFIG_SYS_L2_PL310 > void v7_outer_cache_enable(void) > { > /* Disable the L2 cache */ > @@ -73,6 +76,7 @@ void v7_outer_cache_disable(void) > /* Disable the L2 cache */ > clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); > } > +#endif > > #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ > defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) >
On Thu, 2018-04-19 at 04:47 +0200, Marek Vasut wrote: > On 04/19/2018 11:50 AM, Ley Foon Tan wrote: > > > > Add CONFIG_SYS_L2_PL310 conditional build. > Why ? > In ARM64, L2 cache controller is accessed through processor registers. Hence we shall make this conditional in order this file can be shared across SOCFPGAs. Thanks Chin Liang
On 04/19/2018 07:15 AM, See, Chin Liang wrote: > On Thu, 2018-04-19 at 04:47 +0200, Marek Vasut wrote: >> On 04/19/2018 11:50 AM, Ley Foon Tan wrote: >>> >>> Add CONFIG_SYS_L2_PL310 conditional build. >> Why ? >> > > In ARM64, L2 cache controller is accessed through processor registers. > Hence we shall make this conditional in order this file can be shared > across SOCFPGAs. That should be in the patch description . Do you ever add the PL310 register access on S10 later in the set?
On Thu, Apr 19, 2018 at 4:19 PM, Marek Vasut <marex@denx.de> wrote: > On 04/19/2018 07:15 AM, See, Chin Liang wrote: >> On Thu, 2018-04-19 at 04:47 +0200, Marek Vasut wrote: >>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote: >>>> >>>> Add CONFIG_SYS_L2_PL310 conditional build. >>> Why ? >>> >> >> In ARM64, L2 cache controller is accessed through processor registers. >> Hence we shall make this conditional in order this file can be shared >> across SOCFPGAs. > > That should be in the patch description . > Do you ever add the PL310 register access on S10 later in the set? > > -- Okay, will update description. No, S10 doesn't use PL310 registers. Thanks. Regards Ley Foon
On 04/20/2018 09:49 AM, Ley Foon Tan wrote: > On Thu, Apr 19, 2018 at 4:19 PM, Marek Vasut <marex@denx.de> wrote: >> On 04/19/2018 07:15 AM, See, Chin Liang wrote: >>> On Thu, 2018-04-19 at 04:47 +0200, Marek Vasut wrote: >>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote: >>>>> >>>>> Add CONFIG_SYS_L2_PL310 conditional build. >>>> Why ? >>>> >>> >>> In ARM64, L2 cache controller is accessed through processor registers. >>> Hence we shall make this conditional in order this file can be shared >>> across SOCFPGAs. >> >> That should be in the patch description . >> Do you ever add the PL310 register access on S10 later in the set? >> >> -- > Okay, will update description. > No, S10 doesn't use PL310 registers. If this PL310 is Gen5 specific, then keep it in some Gen5 file.
On Fri, Apr 20, 2018 at 7:00 PM, Marek Vasut <marex@denx.de> wrote: > On 04/20/2018 09:49 AM, Ley Foon Tan wrote: >> On Thu, Apr 19, 2018 at 4:19 PM, Marek Vasut <marex@denx.de> wrote: >>> On 04/19/2018 07:15 AM, See, Chin Liang wrote: >>>> On Thu, 2018-04-19 at 04:47 +0200, Marek Vasut wrote: >>>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote: >>>>>> >>>>>> Add CONFIG_SYS_L2_PL310 conditional build. >>>>> Why ? >>>>> >>>> >>>> In ARM64, L2 cache controller is accessed through processor registers. >>>> Hence we shall make this conditional in order this file can be shared >>>> across SOCFPGAs. >>> >>> That should be in the patch description . >>> Do you ever add the PL310 register access on S10 later in the set? >>> >>> -- >> Okay, will update description. >> No, S10 doesn't use PL310 registers. > > If this PL310 is Gen5 specific, then keep it in some Gen5 file. > > -- > Best regards, > Marek Vasut. Arria 10 needs this PL310 as well. So, we keep it in common misc. Regards Ley Foon
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 692466c..01f824c 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -23,8 +23,10 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SYS_L2_PL310 static const struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; +#endif struct bsel bsel_str[] = { { "rsvd", "Reserved", }, @@ -53,6 +55,7 @@ void enable_caches(void) #endif } +#ifdef CONFIG_SYS_L2_PL310 void v7_outer_cache_enable(void) { /* Disable the L2 cache */ @@ -73,6 +76,7 @@ void v7_outer_cache_disable(void) /* Disable the L2 cache */ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } +#endif #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)