Patchwork [U-Boot] Add flexbus support for Freescale Coldfire 5235

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Submitter Jate Sujjavanich
Date April 5, 2011, 9:29 p.m.
Message ID <6C2434209962DC46B88345CA85C334A2A44B0014FB@Courier.syntech.org>
Download mbox | patch
Permalink /patch/89930/
State Changes Requested
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Comments

Jate Sujjavanich - April 5, 2011, 9:29 p.m.
Add flexbus support for Freescale Coldfire 5235

Signed-off-by Jate Sujjavanich<jate.sujjavanich@myfuelmaster.com>
Jin Zhengxiong-R64188 - Aug. 22, 2011, 8:48 a.m.
> -----Original Message-----
> From: Jate Sujjavanich [mailto:Jate.Sujjavanich@myfuelmaster.com]
> Sent: Wednesday, April 06, 2011 5:30 AM
> To: 'u-boot@lists.denx.de'
> Cc: Jin Zhengxiong-R64188; Jin Zhengxiong-R64188
> Subject: [PATCH] Add flexbus support for Freescale Coldfire 5235
> 
> Add flexbus support for Freescale Coldfire 5235
> 
> Signed-off-by Jate Sujjavanich<jate.sujjavanich@myfuelmaster.com>
> 
> --- u-boot-denx/arch/m68k/include/asm/coldfire/flexbus.h	2011-03-02
> 11:02:14.000000000 -0500
> +++ u-boot/include/asm-m68k/coldfire/flexbus.h	2011-03-25
> 11:42:46.000000000 -0400
> @@ -94,6 +94,12 @@
>  #endif
>  #define FBCS_CSMR_V			(0x00000001)	/* Valid bit */
> 
> +#ifdef CONFIG_M5235
> +#define FBCS_CSCR_SRWS(x)		(((x) & 0x3) << 14)
> +#define FBCS_CSCR_IWS(x)		(((x) & 0xF) << 10)
> +#define FBCS_CSCR_SWWS(x)		(((x) & 0x7) << 0)
> +#endif
> +
>  #define FBCS_CSCR_SWS(x)		(((x) & 0x3F) << 26)
>  #define FBCS_CSCR_SWS_MASK		(0x03FFFFFF)
>  #define FBCS_CSCR_SWSEN			(0x00800000)
> 
Dear Jate Sujjavanich,

Please use git to generate the patch and following the instruction in
http://www.denx.de/wiki/U-Boot/Patches
to send the patch.

Thanks

Best Regards,
Jason

Patch

--- u-boot-denx/arch/m68k/include/asm/coldfire/flexbus.h	2011-03-02 11:02:14.000000000 -0500
+++ u-boot/include/asm-m68k/coldfire/flexbus.h	2011-03-25 11:42:46.000000000 -0400
@@ -94,6 +94,12 @@ 
 #endif
 #define FBCS_CSMR_V			(0x00000001)	/* Valid bit */
 
+#ifdef CONFIG_M5235
+#define FBCS_CSCR_SRWS(x)		(((x) & 0x3) << 14)
+#define FBCS_CSCR_IWS(x)		(((x) & 0xF) << 10)
+#define FBCS_CSCR_SWWS(x)		(((x) & 0x7) << 0)
+#endif
+
 #define FBCS_CSCR_SWS(x)		(((x) & 0x3F) << 26)
 #define FBCS_CSCR_SWS_MASK		(0x03FFFFFF)
 #define FBCS_CSCR_SWSEN			(0x00800000)