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[for-2.12] target/arm: Report unsupported MPU region sizes more clearly

Message ID 20180405172554.27401-1-peter.maydell@linaro.org
State New
Headers show
Series [for-2.12] target/arm: Report unsupported MPU region sizes more clearly | expand

Commit Message

Peter Maydell April 5, 2018, 5:25 p.m. UTC
Currently our PMSAv7 and ARMv7M MPU implementation cannot handle
MPU region sizes smaller than our TARGET_PAGE_SIZE. However we
report that in a slightly confusing way:

 DRSR[3]: No support for MPU (sub)region alignment of 9 bits. Minimum is 10

The problem is not the alignment of the region, but its size;
tweak the error message to say so:
 DRSR[3]: No support for MPU (sub)region size of 512 bytes. Minimum is 1024.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
This doesn't really need to go into 2.12, but as a cleanup to a warning
message it's pretty harmless.

 target/arm/helper.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Philippe Mathieu-Daudé April 5, 2018, 5:36 p.m. UTC | #1
On 04/05/2018 02:25 PM, Peter Maydell wrote:
> Currently our PMSAv7 and ARMv7M MPU implementation cannot handle
> MPU region sizes smaller than our TARGET_PAGE_SIZE. However we
> report that in a slightly confusing way:
> 
>  DRSR[3]: No support for MPU (sub)region alignment of 9 bits. Minimum is 10
> 
> The problem is not the alignment of the region, but its size;
> tweak the error message to say so:
>  DRSR[3]: No support for MPU (sub)region size of 512 bytes. Minimum is 1024.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
> This doesn't really need to go into 2.12, but as a cleanup to a warning
> message it's pretty harmless.
> 
>  target/arm/helper.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index dcb8476d9e..b14fdab140 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -9625,9 +9625,9 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
>              }
>              if (rsize < TARGET_PAGE_BITS) {
>                  qemu_log_mask(LOG_UNIMP,
> -                              "DRSR[%d]: No support for MPU (sub)region "
> -                              "alignment of %" PRIu32 " bits. Minimum is %d\n",
> -                              n, rsize, TARGET_PAGE_BITS);
> +                              "DRSR[%d]: No support for MPU (sub)region size of"
> +                              " %" PRIu32 " bytes. Minimum is %d.\n",
> +                              n, (1 << rsize), TARGET_PAGE_SIZE);
>                  continue;
>              }
>              if (srdis) {
>
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Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index dcb8476d9e..b14fdab140 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9625,9 +9625,9 @@  static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
             }
             if (rsize < TARGET_PAGE_BITS) {
                 qemu_log_mask(LOG_UNIMP,
-                              "DRSR[%d]: No support for MPU (sub)region "
-                              "alignment of %" PRIu32 " bits. Minimum is %d\n",
-                              n, rsize, TARGET_PAGE_BITS);
+                              "DRSR[%d]: No support for MPU (sub)region size of"
+                              " %" PRIu32 " bytes. Minimum is %d.\n",
+                              n, (1 << rsize), TARGET_PAGE_SIZE);
                 continue;
             }
             if (srdis) {