| Message ID | 21d84c6b62fc0b311e2773df939f22d6ee75878f.1522247420.git.michal.simek@xilinx.com |
|---|---|
| State | Accepted |
| Commit | 31bcb3444cbd5002ca9d8f6a3a2644092748cdba |
| Delegated to: | Michal Simek |
| Headers | show |
| Series | fpga: zynqmp: Fpga changes | expand |
On 03/28/2018 04:30 PM, Michal Simek wrote: > From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> > > Xilfpga library expects the size of bitstream in a pointer > but currenly we are passing the size as a value. This patch > fixes this issue. This breaks fpga loadb on zynqmp with FSBL 0.3 for me, so please revert. The commit message is not clear on what the "issue" is or whether the FSBL version has any relevance or whether the ABI changed somewhere in the xilinx blobs, but it is clear reverting this patch fixes an issue for me. > Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> > Signed-off-by: Nava kishore Manne <navam@xilinx.com> > Signed-off-by: Michal Simek <michal.simek@xilinx.com> > --- > > drivers/fpga/zynqmppl.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c > index aae0efc7348e..43e8b2520e35 100644 > --- a/drivers/fpga/zynqmppl.c > +++ b/drivers/fpga/zynqmppl.c > @@ -11,6 +11,7 @@ > #include <zynqmppl.h> > #include <linux/sizes.h> > #include <asm/arch/sys_proto.h> > +#include <memalign.h> > > #define DUMMY_WORD 0xffffffff > > @@ -195,6 +196,7 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf, > static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, > bitstream_type bstype) > { > + ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1); > u32 swap; > ulong bin_buf; > int ret; > @@ -205,15 +207,17 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, > return FPGA_FAIL; > > bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap); > + bsizeptr = (u32 *)&bsize; > > debug("%s called!\n", __func__); > flush_dcache_range(bin_buf, bin_buf + bsize); > + flush_dcache_range((ulong)bsizeptr, (ulong)bsizeptr + sizeof(size_t)); This will trigger unaligned cache flush warning, FYI. And the buffer is u32, while here you use size_t. > buf_lo = (u32)bin_buf; > buf_hi = upper_32_bits(bin_buf); > bstype |= BIT(ZYNQMP_FPGA_BIT_NS); > - ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize, > - bstype, ret_payload); > + ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, > + (u32)(uintptr_t)bsizeptr, bstype, ret_payload); > if (ret) > debug("PL FPGA LOAD fail\n"); > >
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index aae0efc7348e..43e8b2520e35 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -11,6 +11,7 @@ #include <zynqmppl.h> #include <linux/sizes.h> #include <asm/arch/sys_proto.h> +#include <memalign.h> #define DUMMY_WORD 0xffffffff @@ -195,6 +196,7 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf, static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, bitstream_type bstype) { + ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1); u32 swap; ulong bin_buf; int ret; @@ -205,15 +207,17 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, return FPGA_FAIL; bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap); + bsizeptr = (u32 *)&bsize; debug("%s called!\n", __func__); flush_dcache_range(bin_buf, bin_buf + bsize); + flush_dcache_range((ulong)bsizeptr, (ulong)bsizeptr + sizeof(size_t)); buf_lo = (u32)bin_buf; buf_hi = upper_32_bits(bin_buf); bstype |= BIT(ZYNQMP_FPGA_BIT_NS); - ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize, - bstype, ret_payload); + ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, + (u32)(uintptr_t)bsizeptr, bstype, ret_payload); if (ret) debug("PL FPGA LOAD fail\n");