| Message ID | 1519644458-26869-1-git-send-email-al.kochet@gmail.com |
|---|---|
| State | Accepted |
| Commit | 6b0c26fa05470b939be05ecf534566aef0f5a2b2 |
| Delegated to: | Philipp Tomsich |
| Headers | show |
| Series | [U-Boot] rockchip: clk: rk3188: update dpll settings to make EMAC work | expand |
Kever, please review. Thanks, Philipp. > On 26 Feb 2018, at 12:27, Alexander Kochetkov <al.kochet@gmail.com> wrote: > > The patch set dpll settings for 300MHz to values used by binary > blob[1]. With new values dpll still generate 300MHz clock, but > EMAC work. Probably with new values dpll generate more stable clock. > > dpll on rk3188 provide clocks to DDR and EMAC. With current > dpll settings EMAC doesn't work on radxa rock. EMAC sends packets > to network, but it doesn't receive anything. ifconfig shows a lot > of framing errors. > > [1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/ > tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin > > Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> > --- > drivers/clk/rockchip/clk_rk3188.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c > index 6451c95..f674e60 100644 > --- a/drivers/clk/rockchip/clk_rk3188.c > +++ b/drivers/clk/rockchip/clk_rk3188.c > @@ -123,7 +123,7 @@ static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, > unsigned int hz, bool has_bwadj) > { > static const struct pll_div dpll_cfg[] = { > - {.nf = 25, .nr = 2, .no = 1}, > + {.nf = 75, .nr = 1, .no = 6}, > {.nf = 400, .nr = 9, .no = 2}, > {.nf = 500, .nr = 9, .no = 2}, > {.nf = 100, .nr = 3, .no = 1}, > -- > 1.7.9.5 >
> The patch set dpll settings for 300MHz to values used by binary > blob[1]. With new values dpll still generate 300MHz clock, but > EMAC work. Probably with new values dpll generate more stable clock. > > dpll on rk3188 provide clocks to DDR and EMAC. With current > dpll settings EMAC doesn't work on radxa rock. EMAC sends packets > to network, but it doesn't receive anything. ifconfig shows a lot > of framing errors. > > [1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/ > tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin > > Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> > --- > drivers/clk/rockchip/clk_rk3188.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> The patch set dpll settings for 300MHz to values used by binary > blob[1]. With new values dpll still generate 300MHz clock, but > EMAC work. Probably with new values dpll generate more stable clock. > > dpll on rk3188 provide clocks to DDR and EMAC. With current > dpll settings EMAC doesn't work on radxa rock. EMAC sends packets > to network, but it doesn't receive anything. ifconfig shows a lot > of framing errors. > > [1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/ > tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin > > Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> > --- > drivers/clk/rockchip/clk_rk3188.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> The patch set dpll settings for 300MHz to values used by binary > blob[1]. With new values dpll still generate 300MHz clock, but > EMAC work. Probably with new values dpll generate more stable clock. > > dpll on rk3188 provide clocks to DDR and EMAC. With current > dpll settings EMAC doesn't work on radxa rock. EMAC sends packets > to network, but it doesn't receive anything. ifconfig shows a lot > of framing errors. > > [1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/ > tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin > > Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> > Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> > --- > drivers/clk/rockchip/clk_rk3188.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Applied to u-boot-rockchip, thanks!
Hi Philipp, Sorry for reply so late. On 02/26/2018 07:28 PM, Dr. Philipp Tomsich wrote: > Kever, > > please review. > > Thanks, > Philipp. > >> On 26 Feb 2018, at 12:27, Alexander Kochetkov <al.kochet@gmail.com> wrote: >> >> The patch set dpll settings for 300MHz to values used by binary >> blob[1]. With new values dpll still generate 300MHz clock, but >> EMAC work. Probably with new values dpll generate more stable clock. >> >> dpll on rk3188 provide clocks to DDR and EMAC. With current >> dpll settings EMAC doesn't work on radxa rock. EMAC sends packets >> to network, but it doesn't receive anything. ifconfig shows a lot >> of framing errors. >> >> [1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/ >> tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin >> >> Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> >> --- >> drivers/clk/rockchip/clk_rk3188.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c >> index 6451c95..f674e60 100644 >> --- a/drivers/clk/rockchip/clk_rk3188.c >> +++ b/drivers/clk/rockchip/clk_rk3188.c >> @@ -123,7 +123,7 @@ static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, >> unsigned int hz, bool has_bwadj) >> { >> static const struct pll_div dpll_cfg[] = { >> - {.nf = 25, .nr = 2, .no = 1}, >> + {.nf = 75, .nr = 1, .no = 6}, Rockchip always prefer to use nr=1 even if we can only get a frequency close to target frequency, because this setting can get smaller jitter. Some of IP like jitter may very sensitive to this setting. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Thanks, - Kever >> {.nf = 400, .nr = 9, .no = 2}, >> {.nf = 500, .nr = 9, .no = 2}, >> {.nf = 100, .nr = 3, .no = 1}, >> -- >> 1.7.9.5 >> >
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index 6451c95..f674e60 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -123,7 +123,7 @@ static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, unsigned int hz, bool has_bwadj) { static const struct pll_div dpll_cfg[] = { - {.nf = 25, .nr = 2, .no = 1}, + {.nf = 75, .nr = 1, .no = 6}, {.nf = 400, .nr = 9, .no = 2}, {.nf = 500, .nr = 9, .no = 2}, {.nf = 100, .nr = 3, .no = 1},
The patch set dpll settings for 300MHz to values used by binary blob[1]. With new values dpll still generate 300MHz clock, but EMAC work. Probably with new values dpll generate more stable clock. dpll on rk3188 provide clocks to DDR and EMAC. With current dpll settings EMAC doesn't work on radxa rock. EMAC sends packets to network, but it doesn't receive anything. ifconfig shows a lot of framing errors. [1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/ tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> --- drivers/clk/rockchip/clk_rk3188.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)