mbox

[PULL,00/14] ppc-for-2.12 queue 20180216

Message ID 20180216100617.25265-1-david@gibson.dropbear.id.au
State New
Headers show

Pull-request

git://github.com/dgibson/qemu.git tags/ppc-for-2.12-20180216

Message

David Gibson Feb. 16, 2018, 10:06 a.m. UTC 
The following changes since commit cc5a0ae03e0d011521ca5b32d3995a299b6b3ad3:

  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180215-1' into staging (2018-02-15 18:37:46 +0000)

are available in the Git repository at:

  git://github.com/dgibson/qemu.git tags/ppc-for-2.12-20180216

for you to fetch changes up to 58d5b22bbd505dc942d137d5d3da89ad9bc16c0a:

  ppc4xx: Add device models found in PPC440 core SoCs (2018-02-16 14:06:07 +1100)

----------------------------------------------------------------
ppc patch queue 2018-02-16

Highlights of this batch:
  * Conversion to TranslatorOps (Emilio Cota)
  * Further bugfixes and cleanups to vcpu id allocation for pseries
    (Greg Kurz)
  * Another bugfix for HPT resizing (Daniel Henrique-Barboza)
  * Macintosh CUDA cleanups (Mark Cave-Ayland)
  * Further tweaks to Spectre/Meltdown mitigations (Suraj Singh)

----------------------------------------------------------------
BALATON Zoltan (1):
      ppc4xx: Add device models found in PPC440 core SoCs

Daniel Henrique Barboza (1):
      hw/ppc/spapr_hcall: set htab_shift after kvmppc_resize_hpt_commit

Emilio G. Cota (2):
      target/ppc: convert to DisasContextBase
      target/ppc: convert to TranslatorOps

Greg Kurz (4):
      spapr: use spapr->vsmt to compute VCPU ids
      spapr: move VCPU calculation to core machine code
      spapr: rename spapr_vcpu_id() to spapr_get_vcpu_id()
      spapr: consolidate the VCPU id numbering logic in a single place

Laurent Vivier (1):
      hw/char: remove legacy interface escc_init()

Mark Cave-Ayland (3):
      cuda: convert to use the shared mos6522 device
      ppc: move CUDAState and other CUDA-related definitions into separate cuda.h file
      cuda: convert to trace-events

Suraj Jitindar Singh (2):
      ppc/spapr-caps: Change migration macro to take full spapr-cap name
      ppc/spapr-caps: Disallow setting workaround for spapr-cap-ibs

 Makefile.objs                       |    1 +
 hw/char/escc.c                      |  209 ++-----
 hw/misc/macio/cuda.c                |  649 ++++++--------------
 hw/misc/macio/macio.c               |    1 +
 hw/misc/macio/trace-events          |   11 +
 hw/ppc/mac.h                        |   76 +--
 hw/ppc/mac_newworld.c               |   19 +-
 hw/ppc/mac_oldworld.c               |   19 +-
 hw/ppc/ppc440.h                     |   26 +
 hw/ppc/ppc440_uc.c                  | 1159 +++++++++++++++++++++++++++++++++++
 hw/ppc/spapr.c                      |   75 ++-
 hw/ppc/spapr_caps.c                 |   36 +-
 hw/ppc/spapr_cpu_core.c             |    9 +-
 hw/ppc/spapr_hcall.c                |   12 +-
 hw/sparc/sun4m.c                    |   34 +-
 include/hw/char/escc.h              |   54 +-
 include/hw/misc/macio/cuda.h        |  107 ++++
 include/hw/pci/pcie_host.h          |    2 +-
 include/hw/ppc/spapr.h              |    3 +-
 target/ppc/translate.c              |  388 ++++++------
 target/ppc/translate/dfp-impl.inc.c |   16 +-
 target/ppc/translate_init.c         |   32 +-
 22 files changed, 1960 insertions(+), 978 deletions(-)
 create mode 100644 hw/misc/macio/trace-events
 create mode 100644 hw/ppc/ppc440.h
 create mode 100644 hw/ppc/ppc440_uc.c
 create mode 100644 include/hw/misc/macio/cuda.h

Comments

Peter Maydell Feb. 16, 2018, 3:55 p.m. UTC | #1 
On 16 February 2018 at 10:06, David Gibson <david@gibson.dropbear.id.au> wrote:
> The following changes since commit cc5a0ae03e0d011521ca5b32d3995a299b6b3ad3:
>
>   Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180215-1' into staging (2018-02-15 18:37:46 +0000)
>
> are available in the Git repository at:
>
>   git://github.com/dgibson/qemu.git tags/ppc-for-2.12-20180216
>
> for you to fetch changes up to 58d5b22bbd505dc942d137d5d3da89ad9bc16c0a:
>
>   ppc4xx: Add device models found in PPC440 core SoCs (2018-02-16 14:06:07 +1100)
>
> ----------------------------------------------------------------
> ppc patch queue 2018-02-16
>
> Highlights of this batch:
>   * Conversion to TranslatorOps (Emilio Cota)
>   * Further bugfixes and cleanups to vcpu id allocation for pseries
>     (Greg Kurz)
>   * Another bugfix for HPT resizing (Daniel Henrique-Barboza)
>   * Macintosh CUDA cleanups (Mark Cave-Ayland)
>   * Further tweaks to Spectre/Meltdown mitigations (Suraj Singh)
>

Applied, thanks.

-- PMM
Peter Maydell April 27, 2018, 12:38 p.m. UTC | #2 
On 16 February 2018 at 10:06, David Gibson <david@gibson.dropbear.id.au> wrote:
> From: BALATON Zoltan <balaton@eik.bme.hu>
>
> These devices are found in newer SoCs based on 440 core e.g. the 460EX
> (http://www.embeddeddeveloper.com/assets/processors/amcc/datasheets/
> PP460EX_DS2063.pdf)
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---

> +static target_ulong sdram_size(uint32_t bcr)
> +{
> +    target_ulong size;
> +    int sh;
> +
> +    sh = 1024 - ((bcr >> 6) & 0x3ff);
> +    if (sh == 0) {
> +        size = -1;
> +    } else {
> +        size = 8 * M_BYTE * sh;
> +    }
> +
> +    return size;
> +}

Hi. Coverity (CID 1390588) points out that the calculation
"1024 - ((bcr >> 6) & 0x3ff" must result in a value of sh
between 1 and 1024, and therefore the "sh == 0" branch of
the if() is dead code.

Is there an error in the size calculation here?

thanks
-- PMM
BALATON Zoltan April 27, 2018, 9:50 p.m. UTC | #3 
On Fri, 27 Apr 2018, Peter Maydell wrote:
> On 16 February 2018 at 10:06, David Gibson <david@gibson.dropbear.id.au> wrote:
>> From: BALATON Zoltan <balaton@eik.bme.hu>
>>
>> These devices are found in newer SoCs based on 440 core e.g. the 460EX
>> (http://www.embeddeddeveloper.com/assets/processors/amcc/datasheets/
>> PP460EX_DS2063.pdf)
>>
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
>> ---
>
>> +static target_ulong sdram_size(uint32_t bcr)
>> +{
>> +    target_ulong size;
>> +    int sh;
>> +
>> +    sh = 1024 - ((bcr >> 6) & 0x3ff);
>> +    if (sh == 0) {
>> +        size = -1;
>> +    } else {
>> +        size = 8 * M_BYTE * sh;
>> +    }
>> +
>> +    return size;
>> +}
>
> Hi. Coverity (CID 1390588) points out that the calculation
> "1024 - ((bcr >> 6) & 0x3ff" must result in a value of sh
> between 1 and 1024, and therefore the "sh == 0" branch of
> the if() is dead code.
>
> Is there an error in the size calculation here?

Likely this is not entirely correct (see also the FIXME comment in 
sam460ex.c:73) but I still could not obtain the user manual of the SoC 
where I think this is documented so I don't really know what's the correct 
way here and I don't have time at the moment to try to guess from 
accessible sources (such as Linux and U-Boot). So for now I'd leave it as 
it is until I can find out what would be correct here but if the warning 
from Coverity is in your way feel free to patch this to remove the sh == 0 
which should be OK if it can't ever happen.

Regards,
BALATON Zoltan