| Message ID | 1516911131-51397-6-git-send-email-philipp.tomsich@theobroma-systems.com |
|---|---|
| State | Accepted |
| Delegated to: | Philipp Tomsich |
| Headers | show |
| Series | clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates | expand |
> The RK3399 CRU-node assigns rates to a number of clocks that are not > implemented in the RK3399 clock-driver (but which have been > sufficiently initialised from rkclk_init()): for these clocks, we > simply ignore the set_rate() operation and return 0 to signal success. > > Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> > Tested-by: David Wu <david.wu@rock-chips.com> > --- > > Changes in v2: > - Fixed David's email address. > > drivers/clk/rockchip/clk_rk3399.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > Applied to u-boot-rockchip, thanks!
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index e791936..e431ec8 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -883,6 +883,24 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case 0 ... 63: return 0; + + case ACLK_PERIHP: + case HCLK_PERIHP: + case PCLK_PERIHP: + return 0; + + case ACLK_PERILP0: + case HCLK_PERILP0: + case PCLK_PERILP0: + return 0; + + case ACLK_CCI: + return 0; + + case HCLK_PERILP1: + case PCLK_PERILP1: + return 0; + case HCLK_SDMMC: case SCLK_SDMMC: case SCLK_EMMC: