| Message ID | 20180106165843.3461-1-paul@crapouillou.net |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [1/4] pwm: jz4740: Make disable operation compatible with TCU2 mode | expand |
On Sat, Jan 06, 2018 at 05:58:40PM +0100, Paul Cercueil wrote: > From: Maarten ter Huurne <maarten@treewalker.org> > > On the JZ4750 and later SoCs, channel 1 and 2 operate in a different > way (TCU2 mode) as the other channels. If a TCU2 mode counter is > stopped before its PWM functionality is disabled, the output is not > guaranteed to return to the initial level. > > Signed-off-by: Maarten ter Huurne <maarten@treewalker.org> > --- > drivers/pwm/pwm-jz4740.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) Applied patches 1-4, thanks. Thierry
diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c index a75ff3622450..2e41ba213f39 100644 --- a/drivers/pwm/pwm-jz4740.c +++ b/drivers/pwm/pwm-jz4740.c @@ -71,9 +71,15 @@ static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { uint32_t ctrl = jz4740_timer_get_ctrl(pwm->hwpwm); + /* Disable PWM output. + * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the + * counter is stopped, while in TCU1 mode the order does not matter. + */ ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE; - jz4740_timer_disable(pwm->hwpwm); jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); + + /* Stop counter */ + jz4740_timer_disable(pwm->hwpwm); } static int jz4740_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,