| Message ID | 1515205076-14814-3-git-send-email-Anson.Huang@nxp.com |
|---|---|
| State | Superseded |
| Delegated to: | Stefano Babic |
| Headers | show
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dmarc=fail action=none header.from=nxp.com; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BL2FFO11OLC007.mail.protection.outlook.com (10.173.160.142) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.345.12 via Frontend Transport; Sat, 6 Jan 2018 02:34:45 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id w062Z3pp016120; Fri, 5 Jan 2018 19:35:10 -0700 From: Anson Huang <Anson.Huang@nxp.com> To: <sbabic@denx.de>, <fabio.estevam@nxp.com>, <albert.u.boot@aribaud.net>, <troy.kisky@boundarydevices.com>, <christian.gmeiner@gmail.com>, <peng.fan@nxp.com>, <u-boot@lists.denx.de> Date: Sat, 6 Jan 2018 10:17:56 +0800 Message-ID: <1515205076-14814-3-git-send-email-Anson.Huang@nxp.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1515205076-14814-1-git-send-email-Anson.Huang@nxp.com> References: <1515205076-14814-1-git-send-email-Anson.Huang@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131596796858704151; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR03MB2703 X-Mailman-Approved-At: Sat, 06 Jan 2018 15:24:51 +0000 Subject: [U-Boot] [PATCH V2 3/3] imx: mx7: psci: add system power off support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion <u-boot.lists.denx.de> List-Unsubscribe: <https://lists.denx.de/options/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=unsubscribe> List-Archive: <http://lists.denx.de/pipermail/u-boot/> List-Post: <mailto:u-boot@lists.denx.de> List-Help: <mailto:u-boot-request@lists.denx.de?subject=help> List-Subscribe: <https://lists.denx.de/listinfo/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=subscribe> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de> |
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[U-Boot,V2,1/3] mx7_common: use psci 1.0 instead of 0.1
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diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c index 66f6db6..0e515f0 100644 --- a/arch/arm/mach-imx/mx7/psci-mx7.c +++ b/arch/arm/mach-imx/mx7/psci-mx7.c @@ -26,6 +26,12 @@ #define BP_SRC_A7RCR0_A7_CORE_RESET0 0 #define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1 +#define SNVS_LPCR 0x38 +#define BP_SNVS_LPCR_DP_EN 0x20 +#define BP_SNVS_LPCR_TOP 0x40 + +#define CCM_CCGR_SNVS 0x4250 + static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset) { writel(enable, GPC_IPS_BASE_ADDR + offset); @@ -79,3 +85,15 @@ __secure void imx_system_reset(void) { writew(1 << 2, WDOG1_BASE_ADDR); } + +__secure void imx_system_off(void) +{ + u32 val; + + /* make sure SNVS clock is enabled */ + writel(0x3, CCM_BASE_ADDR + CCM_CCGR_SNVS); + + val = readl(SNVS_BASE_ADDR + SNVS_LPCR); + val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP; + writel(val, SNVS_BASE_ADDR + SNVS_LPCR); +} diff --git a/arch/arm/mach-imx/mx7/psci.S b/arch/arm/mach-imx/mx7/psci.S index e23db24..bc2cd8a 100644 --- a/arch/arm/mach-imx/mx7/psci.S +++ b/arch/arm/mach-imx/mx7/psci.S @@ -50,4 +50,11 @@ psci_system_reset: 2: wfi b 2b +.globl psci_system_off +psci_system_off: + bl imx_system_off + +3: wfi + b 3b + .popsection
Add i.MX7 PSCI system power off support, linux kernel can use "poweroff" command to power off system via SNVS, PMIC power will be disabled. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- changes since v1: use "bl" instead of "b" as we need the call to return back. arch/arm/mach-imx/mx7/psci-mx7.c | 18 ++++++++++++++++++ arch/arm/mach-imx/mx7/psci.S | 7 +++++++ 2 files changed, 25 insertions(+)