[U-Boot,RESEND,v2,2/2] arm: mvebu: clearfog: update SPI flash DT description

Message ID 363040f4cc7631e6cab83e80657972c33a28b685.1510549471.git.baruch@tkos.co.il
State Awaiting Upstream
Delegated to: Stefan Roese
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Series
  • [U-Boot,RESEND,v2,1/2] arm: mvebu: clearfog: Fix SPI-NOR flash access
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Commit Message

Baruch Siach Nov. 13, 2017, 5:04 a.m.
All current ClearFog SOMs have the SPI flash populated. Enable SPI flash in
the device tree.

Add an alias to the SPI bus so that the 'sf' command can probe the flash on
bus 1.

Add the "spi-flash" compatible string to make the standard SPI flash driver
probe the device.

Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
v2: Add Jagan's ack
---
 arch/arm/dts/armada-388-clearfog.dts | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

Comments

Stefan Roese Nov. 16, 2017, 1:08 p.m. | #1
On 13.11.2017 06:04, Baruch Siach wrote:
> All current ClearFog SOMs have the SPI flash populated. Enable SPI flash in
> the device tree.
> 
> Add an alias to the SPI bus so that the 'sf' command can probe the flash on
> bus 1.
> 
> Add the "spi-flash" compatible string to make the standard SPI flash driver
> probe the device.
> 
> Reviewed-by: Jagan Teki <jagan@openedev.com>
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
> v2: Add Jagan's ack

Applied to u-boot-marvell/master.

Thanks,
Stefan

Patch

diff --git a/arch/arm/dts/armada-388-clearfog.dts b/arch/arm/dts/armada-388-clearfog.dts
index b2dfd5643521..bc52bc0167d3 100644
--- a/arch/arm/dts/armada-388-clearfog.dts
+++ b/arch/arm/dts/armada-388-clearfog.dts
@@ -61,6 +61,7 @@ 
 		ethernet1 = &eth0;
 		ethernet2 = &eth1;
 		ethernet3 = &eth2;
+		spi1 = &spi1;
 	};
 
 	chosen {
@@ -330,11 +331,9 @@ 
 				status = "okay";
 			};
 
-			spi@10680 {
+			spi1: spi@10680 {
 				/*
-				 * We don't seem to have the W25Q32 on the
-				 * A1 Rev 2.0 boards, so disable SPI.
-				 * CS0: W25Q32 (doesn't appear to be present)
+				 * CS0: W25Q32
 				 * CS1:
 				 * CS2: mikrobus
 				 */
@@ -345,10 +344,9 @@ 
 				spi-flash@0 {
 					#address-cells = <1>;
 					#size-cells = <0>;
-					compatible = "w25q32", "jedec,spi-nor";
+					compatible = "w25q32", "jedec,spi-nor", "spi-flash";
 					reg = <0>; /* Chip select 0 */
 					spi-max-frequency = <3000000>;
-					status = "disabled";
 				};
 			};