Message ID | 20171019201142.28554-1-dan.streetman@canonical.com |
---|---|
State | New |
Headers | show |
Series | [artful,1/2] x86/apic: Silence "FW_BUG TSC_DEADLINE disabled due to Errata" on CPUs without the feature | expand |
Reasonable fixes with clean cherry picks from upstream.
Acked-by: Marcelo Henrique Cerri <marcelo.cerri@canonical.com>
Applied to artful/master-next branch. Thanks.
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 98b3dd8cf2bf..b3273c842850 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -599,9 +599,13 @@ static const struct x86_cpu_id deadline_match[] = { static void apic_check_deadline_errata(void) { - const struct x86_cpu_id *m = x86_match_cpu(deadline_match); + const struct x86_cpu_id *m; u32 rev; + if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) + return; + + m = x86_match_cpu(deadline_match); if (!m) return;