diff mbox series

[U-Boot,1/2] dm: clk: remove CLK() macro for clk_stm32h7

Message ID 1507542084-15068-2-git-send-email-patrice.chotard@st.com
State Accepted
Delegated to: Tom Rini
Headers show
Series STM32H7 clock fixes | expand

Commit Message

Patrice CHOTARD Oct. 9, 2017, 9:41 a.m. UTC 
From: Patrice Chotard <patrice.chotard@st.com>

CLK() macro is a residue of a previously reworked patch,
remove it.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
 drivers/clk/clk_stm32h7.c | 223 ++++++++++++++++++++++------------------------
 1 file changed, 108 insertions(+), 115 deletions(-)

Comments

Vikas MANOCHA Oct. 9, 2017, 4:58 p.m. UTC | #1 
Hi,

> -----Original Message-----
> From: Patrice CHOTARD
> Sent: Monday, October 09, 2017 2:41 AM
> To: u-boot@lists.denx.de; albert.u.boot@aribaud.net; sjg@chromium.org; Vikas MANOCHA <vikas.manocha@st.com>
> Cc: Patrice CHOTARD <patrice.chotard@st.com>; Patrick DELAUNAY <patrick.delaunay@st.com>; Christophe KERELLO
> <christophe.kerello@st.com>
> Subject: [PATCH 1/2] dm: clk: remove CLK() macro for clk_stm32h7
> 
> From: Patrice Chotard <patrice.chotard@st.com>
> 
> CLK() macro is a residue of a previously reworked patch, remove it.
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Reviewed-by: Vikas Manocha <vikas.manocha@st.com>

Cheers,
Vikas

> ---
>  drivers/clk/clk_stm32h7.c | 223 ++++++++++++++++++++++------------------------
>  1 file changed, 108 insertions(+), 115 deletions(-)
> 
> diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c index fd0e3ab..9ca497a 100644
> --- a/drivers/clk/clk_stm32h7.c
> +++ b/drivers/clk/clk_stm32h7.c
> @@ -195,13 +195,6 @@ struct clk_cfg {
>  	const char *name;
>  };
> 
> -#define CLK(_gate_offset, _bit_idx, _name) \ -{ \
> -	.gate_offset = _gate_offset,\
> -	.gate_bit_idx = _bit_idx,\
> -	.name = _name,\
> -}
> -
>  /*
>   * the way all these entries are sorted in this array could seem
>   * unlogical, but we are dependant of kernel DT_bindings, @@ -210,114 +203,114 @@ struct clk_cfg {
>   */
> 
>  static const struct clk_cfg clk_map[] = {
> -	CLK(RCC_AHB3ENR,  31, "d1sram1"),	/* peripheral clocks */
> -	CLK(RCC_AHB3ENR,  30, "itcm"),
> -	CLK(RCC_AHB3ENR,  29, "dtcm2"),
> -	CLK(RCC_AHB3ENR,  28, "dtcm1"),
> -	CLK(RCC_AHB3ENR,   8, "flitf"),
> -	CLK(RCC_AHB3ENR,   5, "jpgdec"),
> -	CLK(RCC_AHB3ENR,   4, "dma2d"),
> -	CLK(RCC_AHB3ENR,   0, "mdma"),
> -	CLK(RCC_AHB1ENR,  28, "usb2ulpi"),
> -	CLK(RCC_AHB1ENR,  17, "eth1rx"),
> -	CLK(RCC_AHB1ENR,  16, "eth1tx"),
> -	CLK(RCC_AHB1ENR,  15, "eth1mac"),
> -	CLK(RCC_AHB1ENR,  14, "art"),
> -	CLK(RCC_AHB1ENR,  26, "usb1ulpi"),
> -	CLK(RCC_AHB1ENR,   1, "dma2"),
> -	CLK(RCC_AHB1ENR,   0, "dma1"),
> -	CLK(RCC_AHB2ENR,  31, "d2sram3"),
> -	CLK(RCC_AHB2ENR,  30, "d2sram2"),
> -	CLK(RCC_AHB2ENR,  29, "d2sram1"),
> -	CLK(RCC_AHB2ENR,   5, "hash"),
> -	CLK(RCC_AHB2ENR,   4, "crypt"),
> -	CLK(RCC_AHB2ENR,   0, "camitf"),
> -	CLK(RCC_AHB4ENR,  28, "bkpram"),
> -	CLK(RCC_AHB4ENR,  25, "hsem"),
> -	CLK(RCC_AHB4ENR,  21, "bdma"),
> -	CLK(RCC_AHB4ENR,  19, "crc"),
> -	CLK(RCC_AHB4ENR,  10, "gpiok"),
> -	CLK(RCC_AHB4ENR,   9, "gpioj"),
> -	CLK(RCC_AHB4ENR,   8, "gpioi"),
> -	CLK(RCC_AHB4ENR,   7, "gpioh"),
> -	CLK(RCC_AHB4ENR,   6, "gpiog"),
> -	CLK(RCC_AHB4ENR,   5, "gpiof"),
> -	CLK(RCC_AHB4ENR,   4, "gpioe"),
> -	CLK(RCC_AHB4ENR,   3, "gpiod"),
> -	CLK(RCC_AHB4ENR,   2, "gpioc"),
> -	CLK(RCC_AHB4ENR,   1, "gpiob"),
> -	CLK(RCC_AHB4ENR,   0, "gpioa"),
> -	CLK(RCC_APB3ENR,   6, "wwdg1"),
> -	CLK(RCC_APB1LENR, 29, "dac12"),
> -	CLK(RCC_APB1LENR, 11, "wwdg2"),
> -	CLK(RCC_APB1LENR,  8, "tim14"),
> -	CLK(RCC_APB1LENR,  7, "tim13"),
> -	CLK(RCC_APB1LENR,  6, "tim12"),
> -	CLK(RCC_APB1LENR,  5, "tim7"),
> -	CLK(RCC_APB1LENR,  4, "tim6"),
> -	CLK(RCC_APB1LENR,  3, "tim5"),
> -	CLK(RCC_APB1LENR,  2, "tim4"),
> -	CLK(RCC_APB1LENR,  1, "tim3"),
> -	CLK(RCC_APB1LENR,  0, "tim2"),
> -	CLK(RCC_APB1HENR,  5, "mdios"),
> -	CLK(RCC_APB1HENR,  4, "opamp"),
> -	CLK(RCC_APB1HENR,  1, "crs"),
> -	CLK(RCC_APB2ENR,  18, "tim17"),
> -	CLK(RCC_APB2ENR,  17, "tim16"),
> -	CLK(RCC_APB2ENR,  16, "tim15"),
> -	CLK(RCC_APB2ENR,   1, "tim8"),
> -	CLK(RCC_APB2ENR,   0, "tim1"),
> -	CLK(RCC_APB4ENR,  26, "tmpsens"),
> -	CLK(RCC_APB4ENR,  16, "rtcapb"),
> -	CLK(RCC_APB4ENR,  15, "vref"),
> -	CLK(RCC_APB4ENR,  14, "comp12"),
> -	CLK(RCC_APB4ENR,   1, "syscfg"),
> -	CLK(RCC_AHB3ENR,  16, "sdmmc1"),	/* kernel clocks */
> -	CLK(RCC_AHB3ENR,  14, "quadspi"),
> -	CLK(RCC_AHB3ENR,  12, "fmc"),
> -	CLK(RCC_AHB1ENR,  27, "usb2otg"),
> -	CLK(RCC_AHB1ENR,  25, "usb1otg"),
> -	CLK(RCC_AHB1ENR,   5, "adc12"),
> -	CLK(RCC_AHB2ENR,   9, "sdmmc2"),
> -	CLK(RCC_AHB2ENR,   6, "rng"),
> -	CLK(RCC_AHB4ENR,  24, "adc3"),
> -	CLK(RCC_APB3ENR,   4, "dsi"),
> -	CLK(RCC_APB3ENR,   3, "ltdc"),
> -	CLK(RCC_APB1LENR, 31, "usart8"),
> -	CLK(RCC_APB1LENR, 30, "usart7"),
> -	CLK(RCC_APB1LENR, 27, "hdmicec"),
> -	CLK(RCC_APB1LENR, 23, "i2c3"),
> -	CLK(RCC_APB1LENR, 22, "i2c2"),
> -	CLK(RCC_APB1LENR, 21, "i2c1"),
> -	CLK(RCC_APB1LENR, 20, "uart5"),
> -	CLK(RCC_APB1LENR, 19, "uart4"),
> -	CLK(RCC_APB1LENR, 18, "usart3"),
> -	CLK(RCC_APB1LENR, 17, "usart2"),
> -	CLK(RCC_APB1LENR, 16, "spdifrx"),
> -	CLK(RCC_APB1LENR, 15, "spi3"),
> -	CLK(RCC_APB1LENR, 14, "spi2"),
> -	CLK(RCC_APB1LENR,  9, "lptim1"),
> -	CLK(RCC_APB1HENR,  8, "fdcan"),
> -	CLK(RCC_APB1HENR,  2, "swp"),
> -	CLK(RCC_APB2ENR,  29, "hrtim"),
> -	CLK(RCC_APB2ENR,  28, "dfsdm1"),
> -	CLK(RCC_APB2ENR,  24, "sai3"),
> -	CLK(RCC_APB2ENR,  23, "sai2"),
> -	CLK(RCC_APB2ENR,  22, "sai1"),
> -	CLK(RCC_APB2ENR,  20, "spi5"),
> -	CLK(RCC_APB2ENR,  13, "spi4"),
> -	CLK(RCC_APB2ENR,  12, "spi1"),
> -	CLK(RCC_APB2ENR,   5, "usart6"),
> -	CLK(RCC_APB2ENR,   4, "usart1"),
> -	CLK(RCC_APB4ENR,  21, "sai4a"),
> -	CLK(RCC_APB4ENR,  21, "sai4b"),
> -	CLK(RCC_APB4ENR,  12, "lptim5"),
> -	CLK(RCC_APB4ENR,  11, "lptim4"),
> -	CLK(RCC_APB4ENR,  10, "lptim3"),
> -	CLK(RCC_APB4ENR,   9, "lptim2"),
> -	CLK(RCC_APB4ENR,   7, "i2c4"),
> -	CLK(RCC_APB4ENR,   5,  "spi6"),
> -	CLK(RCC_APB4ENR,   3, "lpuart1"),
> +	{RCC_AHB3ENR,  31, "d1sram1"},	/* peripheral clocks */
> +	{RCC_AHB3ENR,  30, "itcm"},
> +	{RCC_AHB3ENR,  29, "dtcm2"},
> +	{RCC_AHB3ENR,  28, "dtcm1"},
> +	{RCC_AHB3ENR,   8, "flitf"},
> +	{RCC_AHB3ENR,   5, "jpgdec"},
> +	{RCC_AHB3ENR,   4, "dma2d"},
> +	{RCC_AHB3ENR,   0, "mdma"},
> +	{RCC_AHB1ENR,  28, "usb2ulpi"},
> +	{RCC_AHB1ENR,  17, "eth1rx"},
> +	{RCC_AHB1ENR,  16, "eth1tx"},
> +	{RCC_AHB1ENR,  15, "eth1mac"},
> +	{RCC_AHB1ENR,  14, "art"},
> +	{RCC_AHB1ENR,  26, "usb1ulpi"},
> +	{RCC_AHB1ENR,   1, "dma2"},
> +	{RCC_AHB1ENR,   0, "dma1"},
> +	{RCC_AHB2ENR,  31, "d2sram3"},
> +	{RCC_AHB2ENR,  30, "d2sram2"},
> +	{RCC_AHB2ENR,  29, "d2sram1"},
> +	{RCC_AHB2ENR,   5, "hash"},
> +	{RCC_AHB2ENR,   4, "crypt"},
> +	{RCC_AHB2ENR,   0, "camitf"},
> +	{RCC_AHB4ENR,  28, "bkpram"},
> +	{RCC_AHB4ENR,  25, "hsem"},
> +	{RCC_AHB4ENR,  21, "bdma"},
> +	{RCC_AHB4ENR,  19, "crc"},
> +	{RCC_AHB4ENR,  10, "gpiok"},
> +	{RCC_AHB4ENR,   9, "gpioj"},
> +	{RCC_AHB4ENR,   8, "gpioi"},
> +	{RCC_AHB4ENR,   7, "gpioh"},
> +	{RCC_AHB4ENR,   6, "gpiog"},
> +	{RCC_AHB4ENR,   5, "gpiof"},
> +	{RCC_AHB4ENR,   4, "gpioe"},
> +	{RCC_AHB4ENR,   3, "gpiod"},
> +	{RCC_AHB4ENR,   2, "gpioc"},
> +	{RCC_AHB4ENR,   1, "gpiob"},
> +	{RCC_AHB4ENR,   0, "gpioa"},
> +	{RCC_APB3ENR,   6, "wwdg1"},
> +	{RCC_APB1LENR, 29, "dac12"},
> +	{RCC_APB1LENR, 11, "wwdg2"},
> +	{RCC_APB1LENR,  8, "tim14"},
> +	{RCC_APB1LENR,  7, "tim13"},
> +	{RCC_APB1LENR,  6, "tim12"},
> +	{RCC_APB1LENR,  5, "tim7"},
> +	{RCC_APB1LENR,  4, "tim6"},
> +	{RCC_APB1LENR,  3, "tim5"},
> +	{RCC_APB1LENR,  2, "tim4"},
> +	{RCC_APB1LENR,  1, "tim3"},
> +	{RCC_APB1LENR,  0, "tim2"},
> +	{RCC_APB1HENR,  5, "mdios"},
> +	{RCC_APB1HENR,  4, "opamp"},
> +	{RCC_APB1HENR,  1, "crs"},
> +	{RCC_APB2ENR,  18, "tim17"},
> +	{RCC_APB2ENR,  17, "tim16"},
> +	{RCC_APB2ENR,  16, "tim15"},
> +	{RCC_APB2ENR,   1, "tim8"},
> +	{RCC_APB2ENR,   0, "tim1"},
> +	{RCC_APB4ENR,  26, "tmpsens"},
> +	{RCC_APB4ENR,  16, "rtcapb"},
> +	{RCC_APB4ENR,  15, "vref"},
> +	{RCC_APB4ENR,  14, "comp12"},
> +	{RCC_APB4ENR,   1, "syscfg"},
> +	{RCC_AHB3ENR,  16, "sdmmc1"},	/* kernel clocks */
> +	{RCC_AHB3ENR,  14, "quadspi"},
> +	{RCC_AHB3ENR,  12, "fmc"},
> +	{RCC_AHB1ENR,  27, "usb2otg"},
> +	{RCC_AHB1ENR,  25, "usb1otg"},
> +	{RCC_AHB1ENR,   5, "adc12"},
> +	{RCC_AHB2ENR,   9, "sdmmc2"},
> +	{RCC_AHB2ENR,   6, "rng"},
> +	{RCC_AHB4ENR,  24, "adc3"},
> +	{RCC_APB3ENR,   4, "dsi"},
> +	{RCC_APB3ENR,   3, "ltdc"},
> +	{RCC_APB1LENR, 31, "usart8"},
> +	{RCC_APB1LENR, 30, "usart7"},
> +	{RCC_APB1LENR, 27, "hdmicec"},
> +	{RCC_APB1LENR, 23, "i2c3"},
> +	{RCC_APB1LENR, 22, "i2c2"},
> +	{RCC_APB1LENR, 21, "i2c1"},
> +	{RCC_APB1LENR, 20, "uart5"},
> +	{RCC_APB1LENR, 19, "uart4"},
> +	{RCC_APB1LENR, 18, "usart3"},
> +	{RCC_APB1LENR, 17, "usart2"},
> +	{RCC_APB1LENR, 16, "spdifrx"},
> +	{RCC_APB1LENR, 15, "spi3"},
> +	{RCC_APB1LENR, 14, "spi2"},
> +	{RCC_APB1LENR,  9, "lptim1"},
> +	{RCC_APB1HENR,  8, "fdcan"},
> +	{RCC_APB1HENR,  2, "swp"},
> +	{RCC_APB2ENR,  29, "hrtim"},
> +	{RCC_APB2ENR,  28, "dfsdm1"},
> +	{RCC_APB2ENR,  24, "sai3"},
> +	{RCC_APB2ENR,  23, "sai2"},
> +	{RCC_APB2ENR,  22, "sai1"},
> +	{RCC_APB2ENR,  20, "spi5"},
> +	{RCC_APB2ENR,  13, "spi4"},
> +	{RCC_APB2ENR,  12, "spi1"},
> +	{RCC_APB2ENR,   5, "usart6"},
> +	{RCC_APB2ENR,   4, "usart1"},
> +	{RCC_APB4ENR,  21, "sai4a"},
> +	{RCC_APB4ENR,  21, "sai4b"},
> +	{RCC_APB4ENR,  12, "lptim5"},
> +	{RCC_APB4ENR,  11, "lptim4"},
> +	{RCC_APB4ENR,  10, "lptim3"},
> +	{RCC_APB4ENR,   9, "lptim2"},
> +	{RCC_APB4ENR,   7, "i2c4"},
> +	{RCC_APB4ENR,   5,  "spi6"},
> +	{RCC_APB4ENR,   3, "lpuart1"},
>  };
> 
>  struct stm32_clk {
> --
> 1.9.1
Tom Rini Oct. 17, 2017, 12:47 a.m. UTC | #2 
On Mon, Oct 09, 2017 at 11:41:23AM +0200, patrice.chotard@st.com wrote:

> From: Patrice Chotard <patrice.chotard@st.com>
> 
> CLK() macro is a residue of a previously reworked patch,
> remove it.
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c
index fd0e3ab..9ca497a 100644
--- a/drivers/clk/clk_stm32h7.c
+++ b/drivers/clk/clk_stm32h7.c
@@ -195,13 +195,6 @@  struct clk_cfg {
 	const char *name;
 };
 
-#define CLK(_gate_offset, _bit_idx, _name) \
-{ \
-	.gate_offset = _gate_offset,\
-	.gate_bit_idx = _bit_idx,\
-	.name = _name,\
-}
-
 /*
  * the way all these entries are sorted in this array could seem
  * unlogical, but we are dependant of kernel DT_bindings,
@@ -210,114 +203,114 @@  struct clk_cfg {
  */
 
 static const struct clk_cfg clk_map[] = {
-	CLK(RCC_AHB3ENR,  31, "d1sram1"),	/* peripheral clocks */
-	CLK(RCC_AHB3ENR,  30, "itcm"),
-	CLK(RCC_AHB3ENR,  29, "dtcm2"),
-	CLK(RCC_AHB3ENR,  28, "dtcm1"),
-	CLK(RCC_AHB3ENR,   8, "flitf"),
-	CLK(RCC_AHB3ENR,   5, "jpgdec"),
-	CLK(RCC_AHB3ENR,   4, "dma2d"),
-	CLK(RCC_AHB3ENR,   0, "mdma"),
-	CLK(RCC_AHB1ENR,  28, "usb2ulpi"),
-	CLK(RCC_AHB1ENR,  17, "eth1rx"),
-	CLK(RCC_AHB1ENR,  16, "eth1tx"),
-	CLK(RCC_AHB1ENR,  15, "eth1mac"),
-	CLK(RCC_AHB1ENR,  14, "art"),
-	CLK(RCC_AHB1ENR,  26, "usb1ulpi"),
-	CLK(RCC_AHB1ENR,   1, "dma2"),
-	CLK(RCC_AHB1ENR,   0, "dma1"),
-	CLK(RCC_AHB2ENR,  31, "d2sram3"),
-	CLK(RCC_AHB2ENR,  30, "d2sram2"),
-	CLK(RCC_AHB2ENR,  29, "d2sram1"),
-	CLK(RCC_AHB2ENR,   5, "hash"),
-	CLK(RCC_AHB2ENR,   4, "crypt"),
-	CLK(RCC_AHB2ENR,   0, "camitf"),
-	CLK(RCC_AHB4ENR,  28, "bkpram"),
-	CLK(RCC_AHB4ENR,  25, "hsem"),
-	CLK(RCC_AHB4ENR,  21, "bdma"),
-	CLK(RCC_AHB4ENR,  19, "crc"),
-	CLK(RCC_AHB4ENR,  10, "gpiok"),
-	CLK(RCC_AHB4ENR,   9, "gpioj"),
-	CLK(RCC_AHB4ENR,   8, "gpioi"),
-	CLK(RCC_AHB4ENR,   7, "gpioh"),
-	CLK(RCC_AHB4ENR,   6, "gpiog"),
-	CLK(RCC_AHB4ENR,   5, "gpiof"),
-	CLK(RCC_AHB4ENR,   4, "gpioe"),
-	CLK(RCC_AHB4ENR,   3, "gpiod"),
-	CLK(RCC_AHB4ENR,   2, "gpioc"),
-	CLK(RCC_AHB4ENR,   1, "gpiob"),
-	CLK(RCC_AHB4ENR,   0, "gpioa"),
-	CLK(RCC_APB3ENR,   6, "wwdg1"),
-	CLK(RCC_APB1LENR, 29, "dac12"),
-	CLK(RCC_APB1LENR, 11, "wwdg2"),
-	CLK(RCC_APB1LENR,  8, "tim14"),
-	CLK(RCC_APB1LENR,  7, "tim13"),
-	CLK(RCC_APB1LENR,  6, "tim12"),
-	CLK(RCC_APB1LENR,  5, "tim7"),
-	CLK(RCC_APB1LENR,  4, "tim6"),
-	CLK(RCC_APB1LENR,  3, "tim5"),
-	CLK(RCC_APB1LENR,  2, "tim4"),
-	CLK(RCC_APB1LENR,  1, "tim3"),
-	CLK(RCC_APB1LENR,  0, "tim2"),
-	CLK(RCC_APB1HENR,  5, "mdios"),
-	CLK(RCC_APB1HENR,  4, "opamp"),
-	CLK(RCC_APB1HENR,  1, "crs"),
-	CLK(RCC_APB2ENR,  18, "tim17"),
-	CLK(RCC_APB2ENR,  17, "tim16"),
-	CLK(RCC_APB2ENR,  16, "tim15"),
-	CLK(RCC_APB2ENR,   1, "tim8"),
-	CLK(RCC_APB2ENR,   0, "tim1"),
-	CLK(RCC_APB4ENR,  26, "tmpsens"),
-	CLK(RCC_APB4ENR,  16, "rtcapb"),
-	CLK(RCC_APB4ENR,  15, "vref"),
-	CLK(RCC_APB4ENR,  14, "comp12"),
-	CLK(RCC_APB4ENR,   1, "syscfg"),
-	CLK(RCC_AHB3ENR,  16, "sdmmc1"),	/* kernel clocks */
-	CLK(RCC_AHB3ENR,  14, "quadspi"),
-	CLK(RCC_AHB3ENR,  12, "fmc"),
-	CLK(RCC_AHB1ENR,  27, "usb2otg"),
-	CLK(RCC_AHB1ENR,  25, "usb1otg"),
-	CLK(RCC_AHB1ENR,   5, "adc12"),
-	CLK(RCC_AHB2ENR,   9, "sdmmc2"),
-	CLK(RCC_AHB2ENR,   6, "rng"),
-	CLK(RCC_AHB4ENR,  24, "adc3"),
-	CLK(RCC_APB3ENR,   4, "dsi"),
-	CLK(RCC_APB3ENR,   3, "ltdc"),
-	CLK(RCC_APB1LENR, 31, "usart8"),
-	CLK(RCC_APB1LENR, 30, "usart7"),
-	CLK(RCC_APB1LENR, 27, "hdmicec"),
-	CLK(RCC_APB1LENR, 23, "i2c3"),
-	CLK(RCC_APB1LENR, 22, "i2c2"),
-	CLK(RCC_APB1LENR, 21, "i2c1"),
-	CLK(RCC_APB1LENR, 20, "uart5"),
-	CLK(RCC_APB1LENR, 19, "uart4"),
-	CLK(RCC_APB1LENR, 18, "usart3"),
-	CLK(RCC_APB1LENR, 17, "usart2"),
-	CLK(RCC_APB1LENR, 16, "spdifrx"),
-	CLK(RCC_APB1LENR, 15, "spi3"),
-	CLK(RCC_APB1LENR, 14, "spi2"),
-	CLK(RCC_APB1LENR,  9, "lptim1"),
-	CLK(RCC_APB1HENR,  8, "fdcan"),
-	CLK(RCC_APB1HENR,  2, "swp"),
-	CLK(RCC_APB2ENR,  29, "hrtim"),
-	CLK(RCC_APB2ENR,  28, "dfsdm1"),
-	CLK(RCC_APB2ENR,  24, "sai3"),
-	CLK(RCC_APB2ENR,  23, "sai2"),
-	CLK(RCC_APB2ENR,  22, "sai1"),
-	CLK(RCC_APB2ENR,  20, "spi5"),
-	CLK(RCC_APB2ENR,  13, "spi4"),
-	CLK(RCC_APB2ENR,  12, "spi1"),
-	CLK(RCC_APB2ENR,   5, "usart6"),
-	CLK(RCC_APB2ENR,   4, "usart1"),
-	CLK(RCC_APB4ENR,  21, "sai4a"),
-	CLK(RCC_APB4ENR,  21, "sai4b"),
-	CLK(RCC_APB4ENR,  12, "lptim5"),
-	CLK(RCC_APB4ENR,  11, "lptim4"),
-	CLK(RCC_APB4ENR,  10, "lptim3"),
-	CLK(RCC_APB4ENR,   9, "lptim2"),
-	CLK(RCC_APB4ENR,   7, "i2c4"),
-	CLK(RCC_APB4ENR,   5,  "spi6"),
-	CLK(RCC_APB4ENR,   3, "lpuart1"),
+	{RCC_AHB3ENR,  31, "d1sram1"},	/* peripheral clocks */
+	{RCC_AHB3ENR,  30, "itcm"},
+	{RCC_AHB3ENR,  29, "dtcm2"},
+	{RCC_AHB3ENR,  28, "dtcm1"},
+	{RCC_AHB3ENR,   8, "flitf"},
+	{RCC_AHB3ENR,   5, "jpgdec"},
+	{RCC_AHB3ENR,   4, "dma2d"},
+	{RCC_AHB3ENR,   0, "mdma"},
+	{RCC_AHB1ENR,  28, "usb2ulpi"},
+	{RCC_AHB1ENR,  17, "eth1rx"},
+	{RCC_AHB1ENR,  16, "eth1tx"},
+	{RCC_AHB1ENR,  15, "eth1mac"},
+	{RCC_AHB1ENR,  14, "art"},
+	{RCC_AHB1ENR,  26, "usb1ulpi"},
+	{RCC_AHB1ENR,   1, "dma2"},
+	{RCC_AHB1ENR,   0, "dma1"},
+	{RCC_AHB2ENR,  31, "d2sram3"},
+	{RCC_AHB2ENR,  30, "d2sram2"},
+	{RCC_AHB2ENR,  29, "d2sram1"},
+	{RCC_AHB2ENR,   5, "hash"},
+	{RCC_AHB2ENR,   4, "crypt"},
+	{RCC_AHB2ENR,   0, "camitf"},
+	{RCC_AHB4ENR,  28, "bkpram"},
+	{RCC_AHB4ENR,  25, "hsem"},
+	{RCC_AHB4ENR,  21, "bdma"},
+	{RCC_AHB4ENR,  19, "crc"},
+	{RCC_AHB4ENR,  10, "gpiok"},
+	{RCC_AHB4ENR,   9, "gpioj"},
+	{RCC_AHB4ENR,   8, "gpioi"},
+	{RCC_AHB4ENR,   7, "gpioh"},
+	{RCC_AHB4ENR,   6, "gpiog"},
+	{RCC_AHB4ENR,   5, "gpiof"},
+	{RCC_AHB4ENR,   4, "gpioe"},
+	{RCC_AHB4ENR,   3, "gpiod"},
+	{RCC_AHB4ENR,   2, "gpioc"},
+	{RCC_AHB4ENR,   1, "gpiob"},
+	{RCC_AHB4ENR,   0, "gpioa"},
+	{RCC_APB3ENR,   6, "wwdg1"},
+	{RCC_APB1LENR, 29, "dac12"},
+	{RCC_APB1LENR, 11, "wwdg2"},
+	{RCC_APB1LENR,  8, "tim14"},
+	{RCC_APB1LENR,  7, "tim13"},
+	{RCC_APB1LENR,  6, "tim12"},
+	{RCC_APB1LENR,  5, "tim7"},
+	{RCC_APB1LENR,  4, "tim6"},
+	{RCC_APB1LENR,  3, "tim5"},
+	{RCC_APB1LENR,  2, "tim4"},
+	{RCC_APB1LENR,  1, "tim3"},
+	{RCC_APB1LENR,  0, "tim2"},
+	{RCC_APB1HENR,  5, "mdios"},
+	{RCC_APB1HENR,  4, "opamp"},
+	{RCC_APB1HENR,  1, "crs"},
+	{RCC_APB2ENR,  18, "tim17"},
+	{RCC_APB2ENR,  17, "tim16"},
+	{RCC_APB2ENR,  16, "tim15"},
+	{RCC_APB2ENR,   1, "tim8"},
+	{RCC_APB2ENR,   0, "tim1"},
+	{RCC_APB4ENR,  26, "tmpsens"},
+	{RCC_APB4ENR,  16, "rtcapb"},
+	{RCC_APB4ENR,  15, "vref"},
+	{RCC_APB4ENR,  14, "comp12"},
+	{RCC_APB4ENR,   1, "syscfg"},
+	{RCC_AHB3ENR,  16, "sdmmc1"},	/* kernel clocks */
+	{RCC_AHB3ENR,  14, "quadspi"},
+	{RCC_AHB3ENR,  12, "fmc"},
+	{RCC_AHB1ENR,  27, "usb2otg"},
+	{RCC_AHB1ENR,  25, "usb1otg"},
+	{RCC_AHB1ENR,   5, "adc12"},
+	{RCC_AHB2ENR,   9, "sdmmc2"},
+	{RCC_AHB2ENR,   6, "rng"},
+	{RCC_AHB4ENR,  24, "adc3"},
+	{RCC_APB3ENR,   4, "dsi"},
+	{RCC_APB3ENR,   3, "ltdc"},
+	{RCC_APB1LENR, 31, "usart8"},
+	{RCC_APB1LENR, 30, "usart7"},
+	{RCC_APB1LENR, 27, "hdmicec"},
+	{RCC_APB1LENR, 23, "i2c3"},
+	{RCC_APB1LENR, 22, "i2c2"},
+	{RCC_APB1LENR, 21, "i2c1"},
+	{RCC_APB1LENR, 20, "uart5"},
+	{RCC_APB1LENR, 19, "uart4"},
+	{RCC_APB1LENR, 18, "usart3"},
+	{RCC_APB1LENR, 17, "usart2"},
+	{RCC_APB1LENR, 16, "spdifrx"},
+	{RCC_APB1LENR, 15, "spi3"},
+	{RCC_APB1LENR, 14, "spi2"},
+	{RCC_APB1LENR,  9, "lptim1"},
+	{RCC_APB1HENR,  8, "fdcan"},
+	{RCC_APB1HENR,  2, "swp"},
+	{RCC_APB2ENR,  29, "hrtim"},
+	{RCC_APB2ENR,  28, "dfsdm1"},
+	{RCC_APB2ENR,  24, "sai3"},
+	{RCC_APB2ENR,  23, "sai2"},
+	{RCC_APB2ENR,  22, "sai1"},
+	{RCC_APB2ENR,  20, "spi5"},
+	{RCC_APB2ENR,  13, "spi4"},
+	{RCC_APB2ENR,  12, "spi1"},
+	{RCC_APB2ENR,   5, "usart6"},
+	{RCC_APB2ENR,   4, "usart1"},
+	{RCC_APB4ENR,  21, "sai4a"},
+	{RCC_APB4ENR,  21, "sai4b"},
+	{RCC_APB4ENR,  12, "lptim5"},
+	{RCC_APB4ENR,  11, "lptim4"},
+	{RCC_APB4ENR,  10, "lptim3"},
+	{RCC_APB4ENR,   9, "lptim2"},
+	{RCC_APB4ENR,   7, "i2c4"},
+	{RCC_APB4ENR,   5,  "spi6"},
+	{RCC_APB4ENR,   3, "lpuart1"},
 };
 
 struct stm32_clk {