| Message ID | 20170531235737.11676-11-sjg@chromium.org |
|---|---|
| State | Accepted |
| Delegated to: | Simon Glass |
| Headers | show |
For devices that need a delay between SPI transactions we seem to need an
additional delay before the first one if the CPU is running at full speed.
Add this, under control of the existing setting. At present it will only
be enabled with the Chrome OS EC.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2: None
drivers/spi/tegra114_spi.c | 1 +
1 file changed, 1 insertion(+)
Applied to u-boot-dm, thanks!
diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c index 013bc82380..04b4fce061 100644 --- a/drivers/spi/tegra114_spi.c +++ b/drivers/spi/tegra114_spi.c @@ -149,6 +149,7 @@ static int tegra114_spi_probe(struct udevice *bus) bus->name, priv->freq, rate); } } + udelay(plat->deactivate_delay_us); /* Clear stale status here */ setbits_le32(®s->fifo_status,
For devices that need a delay between SPI transactions we seem to need an additional delay before the first one if the CPU is running at full speed. Add this, under control of the existing setting. At present it will only be enabled with the Chrome OS EC. Signed-off-by: Simon Glass <sjg@chromium.org> --- Changes in v2: None drivers/spi/tegra114_spi.c | 1 + 1 file changed, 1 insertion(+)