Message ID | 20170314175503.7073-2-hauke.mehrtens@intel.com |
---|---|
State | Accepted |
Delegated to: | Hauke Mehrtens |
Headers | show |
On 2017-03-14 18:55, hauke.mehrtens@intel.com wrote: > From: Hauke Mehrtens <hauke.mehrtens@intel.com> > > This can be used to indicate that a target does not support the optional mips16 > extension even when it is a mips32r2 or later CPU. > > This will generate a separate toolchain and a separate package folder, > e.g. mips_24kc_nomips16 Which target needs this? - Felix
On 03/14/2017 10:46 PM, Felix Fietkau wrote: > On 2017-03-14 18:55, hauke.mehrtens@intel.com wrote: >> From: Hauke Mehrtens <hauke.mehrtens@intel.com> >> >> This can be used to indicate that a target does not support the optional mips16 >> extension even when it is a mips32r2 or later CPU. >> >> This will generate a separate toolchain and a separate package folder, >> e.g. mips_24kc_nomips16 > Which target needs this? The Lantiq / Intel GRX350 / GRX550 MIPS interAptiv mips32r3 SoC does not support the MIPS16e ASE. This patch is to get our SDK in sync with upstream LEDE and I am planing in the mid term to also add support for this SoC to LEDE. There are already products with this SoC in the retail market. Hauke
diff --git a/include/target.mk b/include/target.mk index 5490d48..61489ca 100644 --- a/include/target.mk +++ b/include/target.mk @@ -258,7 +258,9 @@ ifeq ($(DUMP),1) FEATURES += virtio endif ifneq ($(CONFIG_CPU_MIPS32_R2),) - FEATURES += mips16 + ifneq ($(CPU_SUBTYPE),nomips16) + FEATURES += mips16 + endif endif FEATURES += $(foreach v,6 7,$(if $(CONFIG_CPU_V$(v)),arm_v$(v)))