Patchwork [U-Boot,3/3] tqm85xx: Update PCI code

mail settings
Submitter Wolfgang Denk
Date Oct. 26, 2010, 7:54 p.m.
Message ID <>
Download mbox | patch
Permalink /patch/71940/
State Superseded
Delegated to: Kumar Gala
Headers show


Wolfgang Denk - Oct. 26, 2010, 7:54 p.m.
Dear Peter Tyser,

In message <> you wrote:
> Update to use the recent, common FSL PCI initialization code.
> Signed-off-by: Peter Tyser <>
> CC:
> ---
>  board/tqc/tqm85xx/law.c     |    4 +-
>  board/tqc/tqm85xx/tlb.c     |   10 ++--
>  board/tqc/tqm85xx/tqm85xx.c |  151 ++++++++++++-------------------------------
>  include/configs/TQM85xx.h   |   20 +++---
>  4 files changed, 59 insertions(+), 126 deletions(-)

This commit needs fixing.

First, it corrupts the output. Some patch like this should be added:

Even worse, we now see a (badly formatted, but this is just an added

	Scanning PCI bus 00
    PCIE1 on bus 00 - 00

which is completely bogus as there on these boards nor on these

Can you please provide a fix?


Best regards,

Wolfgang Denk
Wolfgang Denk - Oct. 27, 2010, 6:47 a.m.
Dear Peter Tyser,

In message <1288156533.1971.6.camel@ptyser-laptop> you wrote:
> Can you send the entire bootup output?  The code is based on Freescale
> reference boards, eg the mpc8568mds, so I'd guess the problem is not
> tqm85xx-specific.

Sure. Here it is:

U-Boot 2010.09-00558-g79e6313 (Oct 26 2010 - 21:31:41)

CPU:   8555E, Version: 1.1, (0x80790011)
Core:  Unknown, Version: 2.0, (0x80200020)
Clock Configuration:
       CPU0:833.333 MHz, 
       CCB:333.333 MHz,
       DDR:166.667 MHz (333.333 MT/s data rate), LBC:41.667 MHz
CPM:   333.333 MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
Board: TQM8555, serial# ABC0555 casl=25
I2C:   ready
DRAM:  128 MiB
FLASH: 128 MiB
L2:    256 KB already enabled

   PCI1:  32 bit, 33 MHz, sync, host, arbiter
               Scanning PCI bus 00
    PCIE1 on bus 00 - 00
PCI-X will only work at 66 MHz
In:    serial
Out:   serial
Err:   serial
DTT:   1 is 41 C
PS/2:  No device found
Kbd:   reset failed, no ACK

Type run flash_nfs to mount root filesystem over NFS

Hit any key to stop autoboot:  0 

Please also note the "Core:  Unknown" which is new.

Best regards,

Wolfgang Denk
Wolfgang Denk - Oct. 28, 2010, 9:20 p.m.
Dear Peter Tyser,

In message <1288298646.8967.130.camel@petert> you wrote:
> So the original behavior of the TQM board was out of sync with the
> majority of other boards, and some boards have a newline.

Let's say a large number of board maintainers do not care about nice
formatting of the output.

So if we use common code for a certain set, please let's not use the
lowest common denominator.

> I agree we should get rid of the newline on all these printfs, but the
> indentation issue is murkier to me.  The common Freescale PCI code
> currently assumes there is an indentation, so we should really sync
> boards'/FSL indentation up to be consistent.  Anyone have a strong
> preference for the indentation?  p2020 way, or socrates way above?

Why should the PCI output be indented? It is not so on any other board
I ever had my fingers on.

Example - all APM boards look like that:

CPU:   AMCC PowerPC 460EX Rev. B at 1066.667 MHz (PLB=266 OPB=88 EBC=88)
       Security/Kasumi support
       Bootstrap Option H - Boot ROM Location I2C (Addr 0x52)
       Internal PCI arbiter enabled
       32 kB I-Cache 32 kB D-Cache
Board: Canyonlands - AMCC PPC460EX Evaluation Board, 1*PCIe/1*SATA, Rev. 16
I2C:   ready
DRAM:  512 MiB (ECC not enabled, 533 MHz, CL4)
NAND:  128 MiB
PCI:   Bus Dev VenId DevId Class Int
PCIE1: link is not up.
DTT:   1 is 27 C
Net:   ppc_4xx_eth0, ppc_4xx_eth1

Output starts in the first column, all nicely aligned.

> >                Scanning PCI bus 00
> >     PCIE1 on bus 00 - 00
> I just sent a patch to address this issue.


Best regards,

Wolfgang Denk


diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c
index 2c3885f..027c429 100644
--- a/board/tqc/tqm85xx/tqm85xx.c
+++ b/board/tqc/tqm85xx/tqm85xx.c
@@ -567,7 +567,7 @@  void pci_init_board (void)
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 		SET_STD_PCI_INFO(pci_info[num], 1);
 		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
-		printf ("\n   PCI1:  %d bit, %s MHz, %s, %s, %s\n",
+		printf ("PCI1:  %d bit, %s MHz, %s, %s, %s\n",
 			(pci_32) ? 32 : 64,
 			(pci_speed == 33333333) ? "33" :
 			(pci_speed == 66666666) ? "66" : "unknown",
@@ -591,7 +591,7 @@  void pci_init_board (void)
 	} else {
-		printf("    PCI1: disabled\n");
+		printf("PCI1:  disabled\n");
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);