diff mbox

[U-Boot,v3,06/11] spi: cadence_qspi: Use spi mode at the point it is needed

Message ID 1480424316-22201-7-git-send-email-phil.edworthy@renesas.com
State Accepted
Commit 7d403f284c814d6df9f1d116e691d6468c75282a
Delegated to: Jagannadha Sutradharudu Teki
Headers show

Commit Message

Phil Edworthy Nov. 29, 2016, 12:58 p.m. UTC 
Instead of extracting mode settings and passing them as separate
args to another function, just pass the SPI mode as an arg.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
---
 v3:
  - New patch introduced to address comments.
---
 drivers/spi/cadence_qspi.c     | 4 +---
 drivers/spi/cadence_qspi.h     | 3 +--
 drivers/spi/cadence_qspi_apb.c | 7 +++----
 3 files changed, 5 insertions(+), 9 deletions(-)

Comments

Jagan Teki Dec. 2, 2016, 2:09 p.m. UTC | #1 
On Tue, Nov 29, 2016 at 6:28 PM, Phil Edworthy
<phil.edworthy@renesas.com> wrote:
> Instead of extracting mode settings and passing them as separate
> args to another function, just pass the SPI mode as an arg.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>

Reviewed-by: Jagan Teki <jagan@openedev.com>

thanks!
diff mbox

Patch

diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 1051afb..55192d6 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -170,14 +170,12 @@  static int cadence_spi_probe(struct udevice *bus)
 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
 {
 	struct cadence_spi_priv *priv = dev_get_priv(bus);
-	unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0;
-	unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0;
 
 	/* Disable QSPI */
 	cadence_qspi_apb_controller_disable(priv->regbase);
 
 	/* Set SPI mode */
-	cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha);
+	cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
 
 	/* Enable QSPI */
 	cadence_qspi_apb_controller_enable(priv->regbase);
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index a849f7b..d1927a4 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -63,8 +63,7 @@  int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
 
 void cadence_qspi_apb_chipselect(void *reg_base,
 	unsigned int chip_select, unsigned int decoder_enable);
-void cadence_qspi_apb_set_clk_mode(void *reg_base_addr,
-	unsigned int clk_pol, unsigned int clk_pha);
+void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
 	unsigned int ref_clk_hz, unsigned int sclk_hz);
 void cadence_qspi_apb_delay(void *reg_base,
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 634a857..e81d678 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -294,8 +294,7 @@  void cadence_qspi_apb_config_baudrate_div(void *reg_base,
 	return;
 }
 
-void cadence_qspi_apb_set_clk_mode(void *reg_base,
-	unsigned int clk_pol, unsigned int clk_pha)
+void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
 {
 	unsigned int reg;
 
@@ -303,9 +302,9 @@  void cadence_qspi_apb_set_clk_mode(void *reg_base,
 	reg = readl(reg_base + CQSPI_REG_CONFIG);
 	reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
 
-	if (clk_pol)
+	if (mode & SPI_CPOL)
 		reg |= CQSPI_REG_CONFIG_CLK_POL;
-	if (clk_pha)
+	if (mode & SPI_CPHA)
 		reg |= CQSPI_REG_CONFIG_CLK_PHA;
 
 	writel(reg, reg_base + CQSPI_REG_CONFIG);