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[U-Boot,v4,2/6] ARMv8: Enable SMC instruction

Message ID 1480070856-4563-3-git-send-email-hongbo.zhang@nxp.com
State Superseded
Delegated to: York Sun
Headers show

Commit Message

macro.wave.z@gmail.com Nov. 25, 2016, 10:47 a.m. UTC
PSCI implementation needs the SMC instruction to be enabled.
Following the legacy codes pattern, no bit macro definition and bit operation
are used, only the immediate data used in line is changed.

Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
 arch/arm/include/asm/macro.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

York Sun Nov. 29, 2016, 8:49 p.m. UTC | #1
On 11/25/2016 02:47 AM, Hongbo Zhang wrote:
> PSCI implementation needs the SMC instruction to be enabled.
> Following the legacy codes pattern, no bit macro definition and bit operation
> are used, only the immediate data used in line is changed.
>
> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>
> ---
>  arch/arm/include/asm/macro.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
> index 9bb0efa..35ea002 100644
> --- a/arch/arm/include/asm/macro.h
> +++ b/arch/arm/include/asm/macro.h
> @@ -137,7 +137,7 @@ lr	.req	x30
>
>  .macro armv8_switch_to_el2_m, xreg1
>  	/* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
> -	mov	\xreg1, #0x5b1
> +	mov	\xreg1, #0x531
>  	msr	scr_el3, \xreg1
>  	msr	cptr_el3, xzr		/* Disable coprocessor traps to EL3 */
>  	mov	\xreg1, #0x33ff
>

Hongbo,

This has a conflict. Please work with Alison Wang to figure out the SMD 
bit as she has changed the code to deal with both 64- and 32-bit. I can 
guess a fix to this conflict, but rather to have her onboard.

York
macro.wave.z@gmail.com Nov. 30, 2016, 9:47 a.m. UTC | #2
OK.

And currently this series are against the community tree, and if this
should go to your tree, I should rebase to yours, right?

On Wed, Nov 30, 2016 at 4:49 AM, york sun <york.sun@nxp.com> wrote:
> On 11/25/2016 02:47 AM, Hongbo Zhang wrote:
>> PSCI implementation needs the SMC instruction to be enabled.
>> Following the legacy codes pattern, no bit macro definition and bit operation
>> are used, only the immediate data used in line is changed.
>>
>> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
>> Reviewed-by: Tom Rini <trini@konsulko.com>
>> ---
>>  arch/arm/include/asm/macro.h | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
>> index 9bb0efa..35ea002 100644
>> --- a/arch/arm/include/asm/macro.h
>> +++ b/arch/arm/include/asm/macro.h
>> @@ -137,7 +137,7 @@ lr        .req    x30
>>
>>  .macro armv8_switch_to_el2_m, xreg1
>>       /* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
>> -     mov     \xreg1, #0x5b1
>> +     mov     \xreg1, #0x531
>>       msr     scr_el3, \xreg1
>>       msr     cptr_el3, xzr           /* Disable coprocessor traps to EL3 */
>>       mov     \xreg1, #0x33ff
>>
>
> Hongbo,
>
> This has a conflict. Please work with Alison Wang to figure out the SMD
> bit as she has changed the code to deal with both 64- and 32-bit. I can
> guess a fix to this conflict, but rather to have her onboard.
>
> York
York Sun Nov. 30, 2016, 4:46 p.m. UTC | #3
On 11/30/2016 01:47 AM, Hongbo Zhang wrote:
> OK.
>
> And currently this series are against the community tree, and if this
> should go to your tree, I should rebase to yours, right?
>

No. Please use upstream master branch. I trye to keep my repo in sync 
but mostly it is behind by several merges.

York
diff mbox

Patch

diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 9bb0efa..35ea002 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -137,7 +137,7 @@  lr	.req	x30
 
 .macro armv8_switch_to_el2_m, xreg1
 	/* 64bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
-	mov	\xreg1, #0x5b1
+	mov	\xreg1, #0x531
 	msr	scr_el3, \xreg1
 	msr	cptr_el3, xzr		/* Disable coprocessor traps to EL3 */
 	mov	\xreg1, #0x33ff