@@ -339,6 +339,24 @@ static void radix_init_amor(void)
mtspr(SPRN_AMOR, amor);
}
+/*
+ * For radix page tables we setup, the IAMR values as follows
+ * IMAR = 0100...00 (key 0 is set to 1)
+ * AMR, UAMR, UAMOR are not affected
+ */
+static void radix_init_iamr(void)
+{
+ unsigned long iamr_mask = 0x4000000000000000;
+ unsigned long iamr = mfspr(SPRN_IAMR);
+
+ if (cpu_has_feature(CPU_FTR_POWER9_DD1))
+ return;
+
+ iamr = iamr_mask;
+
+ mtspr(SPRN_IAMR, iamr);
+}
+
void __init radix__early_init_mmu(void)
{
unsigned long lpcr;
@@ -398,6 +416,7 @@ void __init radix__early_init_mmu(void)
radix_init_amor();
}
+ radix_init_iamr();
radix_init_pgtable();
}
@@ -415,6 +434,7 @@ void radix__early_init_mmu_secondary(void)
__pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
radix_init_amor();
}
+ radix_init_iamr();
}
void radix__mmu_cleanup_all(void)
ISA 3 defines new encoded access authority that allows instruction access prevention in privileged mode and allows normal access to problem state. This patch just enables IAMR (Instruction Authority Mask Register), enabling AMR would require more work. I've tested this with a buggy driver and a simple payload. The payload is specific to the build I've tested. Signed-off-by: Balbir Singh <bsingharora@gmail.com> --- arch/powerpc/mm/pgtable-radix.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)