| Message ID | 20160921101900.31610-13-paul.burton@imgtec.com |
|---|---|
| State | Accepted |
| Commit | c5b8412d60e22b49348a63848cbf7b6ab5ccb16e |
| Delegated to: | Daniel Schwierzeck |
| Headers | show |
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index c157d03..8f85ede 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -127,6 +127,7 @@ reset: and t0, t0, MIPS_CONF_IMPL or t0, t0, CONF_CM_UNCACHED mtc0 t0, CP0_CONFIG + ehb #endif /*
During boot we set Config.K0=2 (uncached) such that any accesses to the kseg0 memory region are performed uncached before the caches are initialised. This write to the Config register introduces an execution hazard between it & any following memory accesses (such as the load of _gp), which we need to clear in order to ensure those memory accesses are actually performed uncached. Clear this execution hazard with the insertion of an ehb execution hazard barrier instruction. Signed-off-by: Paul Burton <paul.burton@imgtec.com> --- Changes in v3: - New patch Changes in v2: None arch/mips/cpu/start.S | 1 + 1 file changed, 1 insertion(+)