| Message ID | 1285629463-27699-3-git-send-email-nacc@us.ibm.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Commit | f56029b5eafda6175be4e5c91ca69c04ccda3661 |
| Headers | show |
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c index 93834b0..7c1e342 100644 --- a/arch/powerpc/platforms/pseries/xics.c +++ b/arch/powerpc/platforms/pseries/xics.c @@ -178,7 +178,7 @@ static int get_irq_server(unsigned int virq, const struct cpumask *cpumask, if (!distribute_irqs) return default_server; - if (!cpumask_equal(cpumask, cpu_all_mask)) { + if (!cpumask_subset(cpu_possible_mask, cpumask)) { int server = cpumask_first_and(cpu_online_mask, cpumask); if (server < nr_cpu_ids)
Current firmware only allows us to send IRQs to the first processor or all processors. We currently check to see if the passed in mask is equal to the all_mask, but the firmware is only considering whether the request is for the equivalent of the possible_mask. Thus, we think the request is for some subset of CPUs and only assign IRQs to the first CPU (on systems without irqbalance running) as evidenced by /proc/interrupts. By using possible_mask instead, we account for this and proper interleaving of interrupts occurs. Without this change and "pseries/xics: use cpu_possible_mask rather than cpu_all_mask", IRQs are all routed to CPU0 on power machines not running irqbalance. Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com> --- arch/powerpc/platforms/pseries/xics.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)