diff mbox

[U-Boot,2/2] armv8: fsl-lsch2: enable snoopable sata read and write

Message ID 1470640040-7920-2-git-send-email-yuantian.tang@nxp.com
State Accepted
Delegated to: York Sun
Headers show

Commit Message

tang yuantian Aug. 8, 2016, 7:07 a.m. UTC 
From: Tang Yuantian <Yuantian.Tang@nxp.com>

By default the SATA IP on the ls1043a/ls1046a SoCs does not generating
coherent/snoopable transactions.  This patch enable it in the SCFG_SNPCNFGCR
register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA controller
nodes.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c                | 5 ++++-
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h         | 1 +
 3 files changed, 7 insertions(+), 1 deletion(-)

Comments

York Sun Oct. 8, 2016, 5:14 p.m. UTC | #1 
On 08/08/2016 12:18 AM, yuantian.tang@nxp.com wrote:
> From: Tang Yuantian <Yuantian.Tang@nxp.com>
>
> By default the SATA IP on the ls1043a/ls1046a SoCs does not generating
> coherent/snoopable transactions.  This patch enable it in the SCFG_SNPCNFGCR
> register along with sata axicc register.
> In addition, the dma-coherent property must be set on the SATA controller
> nodes.
>
> Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
> ---


Applied to fsl-qoriq master, awaiting upstream. Thanks.

York
diff mbox

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6333122..fe13782 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -224,6 +224,7 @@  int sata_init(void)
 
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
 	ahci_init((void __iomem *)CONFIG_SYS_SATA);
 	scsi_scan(0);
@@ -310,7 +311,9 @@  void fsl_lsch2_early_init_f(void)
 #endif
 	/* Make SEC reads and writes snoopable */
 	setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
-		     SCFG_SNPCNFGCR_SECWRSNP);
+		     SCFG_SNPCNFGCR_SECWRSNP |
+		     SCFG_SNPCNFGCR_SATARDSNP |
+		     SCFG_SNPCNFGCR_SATAWRSNP);
 
 	/*
 	 * Enable snoop requests and DVM message requests for
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 95a4293..2d307cc 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -335,6 +335,8 @@  struct ccsr_gur {
 
 #define SCFG_SNPCNFGCR_SECRDSNP		0x80000000
 #define SCFG_SNPCNFGCR_SECWRSNP		0x40000000
+#define SCFG_SNPCNFGCR_SATARDSNP	0x00800000
+#define SCFG_SNPCNFGCR_SATAWRSNP	0x00400000
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index d5fe0ce..f29fd9f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -61,6 +61,7 @@  struct cpu_type {
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG    0xa003fffe
 #define AHCI_PORT_TRANS_CFG    0x08000029
+#define AHCI_PORT_AXICC_CFG	0x3fffffff
 
 /* AHCI (sata) register map */
 struct ccsr_ahci {