diff mbox

[MIPS] Remove "new" MIPS TLS access patterns

Message ID B5E67142681B53468FAF6B7C313565624F4EDCC5@hhmail02.hh.imgtec.org
State New
Headers show

Commit Message

Robert Suchanek May 24, 2016, 2:28 p.m. UTC 
Hi,

The below finishes the revert of r137670 that was already partially reverted
in r137734 as part of PR target/35802.

It would appear that the revert was not completed because of a spill failure
at the time.  As LRA can handle the 'v' constraint just fine and MIPS is going
to drop the support for the classic reload, there is no need for this workaround
that introduces spurious moves hurting the performance.

No regression. Ok to commit?

Regards,
Robert

2016-05-24  Simon Dardis  <simon.dardis@imgtec.com>

gcc/
	* config/mips/constraints.md (V1_REG): Update comment.
	* config/mips/mips.md (get_tls_get_tp_<mode>): Remove.
	(*get_tls_tp_<mode>): Rename.
	* doc/md.texi: Update the MIPS "v" constraint.
---
 gcc/config/mips/constraints.md |  6 +++---
 gcc/config/mips/mips.md        | 26 +++-----------------------
 gcc/doc/md.texi                |  3 +--
 3 files changed, 7 insertions(+), 28 deletions(-)

Comments

Matthew Fortune May 24, 2016, 2:56 p.m. UTC | #1 
Robert Suchanek <Robert.Suchanek@imgtec.com> writes:
> The below finishes the revert of r137670 that was already partially reverted
> in r137734 as part of PR target/35802.
> 
> It would appear that the revert was not completed because of a spill failure
> at the time.  As LRA can handle the 'v' constraint just fine and MIPS is going
> to drop the support for the classic reload, there is no need for this workaround
> that introduces spurious moves hurting the performance.
> 
> No regression. Ok to commit?

This is OK but should wait for a patch to remove the -mlra option and associated
non-lra code.

Thanks,
Matthew
diff mbox

Patch

diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md
index 56b363e..155b212 100644
--- a/gcc/config/mips/constraints.md
+++ b/gcc/config/mips/constraints.md
@@ -60,11 +60,11 @@  (define_register_constraint "e" "LEA_REGS"
 (define_register_constraint "j" "PIC_FN_ADDR_REG"
   "@internal")
 
+;; FIXME: Remove this comment and below once the MIPS backend can
+;; only be used with LRA.
 ;; Don't use this constraint in gcc code!  It runs the risk of
 ;; introducing a spill failure; see tls_get_tp_<mode>.
-(define_register_constraint "v" "V1_REG"
-  "Register @code{$3}.  Do not use this constraint in new code;
-   it is retained only for compatibility with glibc.")
+(define_register_constraint "v" "V1_REG" "@internal")
 
 (define_register_constraint "y" "GR_REGS"
   "Equivalent to @code{r}; retained for backwards compatibility.")
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 527f2e1..432ab1a 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -7386,29 +7386,9 @@  (define_insn "*mips16e_save_restore"
 ;; MIPS 32r2 specification, but we use it on any architecture because
 ;; we expect it to be emulated.  Use .set to force the assembler to
 ;; accept it.
-;;
-;; We do not use a constraint to force the destination to be $3
-;; because $3 can appear explicitly as a function return value.
-;; If we leave the use of $3 implicit in the constraints until
-;; reload, we may end up making a $3 return value live across
-;; the instruction, leading to a spill failure when reloading it.
-(define_insn_and_split "tls_get_tp_<mode>"
-  [(set (match_operand:P 0 "register_operand" "=d")
-	(unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
-   (clobber (reg:P TLS_GET_TP_REGNUM))]
-  "HAVE_AS_TLS && !TARGET_MIPS16"
-  "#"
-  "&& reload_completed"
-  [(set (reg:P TLS_GET_TP_REGNUM)
-	(unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
-   (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
-  ""
-  [(set_attr "type" "unknown")
-   (set_attr "mode" "<MODE>")
-   (set_attr "insn_count" "2")])
 
-(define_insn "*tls_get_tp_<mode>_split"
-  [(set (reg:P TLS_GET_TP_REGNUM)
+(define_insn "tls_get_tp_<mode>"
+  [(set (match_operand:P 0 "register_operand" "=v")
 	(unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
   "HAVE_AS_TLS && !TARGET_MIPS16"
   {
@@ -7418,7 +7398,7 @@  (define_insn "*tls_get_tp_<mode>_split"
     return ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop";
   }
   [(set_attr "type" "unknown")
-   ; Since rdhwr always generates a trap for now, putting it in a delay
+   ; Since rdhwr may generate a trap, putting it in a delay
    ; slot would make the kernel's emulation of it much slower.
    (set_attr "can_delay" "no")
    (set_attr "mode" "<MODE>")])
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index f2360c8..d1c88d2 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -2705,8 +2705,7 @@  A register suitable for use in an indirect jump.  This will always be
 @code{$25} for @option{-mabicalls}.
 
 @item v
-Register @code{$3}.  Do not use this constraint in new code;
-it is retained only for compatibility with glibc.
+Register @code{$3}.  The register for acquiring the TLS pointer.
 
 @item y
 Equivalent to @code{r}; retained for backwards compatibility.