From patchwork Tue May 24 14:28:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Suchanek X-Patchwork-Id: 625684 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rDd7C6DQ7z9t4g for ; Wed, 25 May 2016 00:28:23 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=CJiupZG9; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=jam artfT/qHwep8KYWymFG8PprS6eu0bscI+y8N8GCsqP/Mi/pVSjecF5DfCOgEybQ2 lBC/aycnKAAcDeZdZz60HY1PGmCpsaG9sPg2hVebWwjfpmFTszY+iuzfi7nQO3DZ WjQZuTjLEfug5R/4tNtA2y/TzoPh5WT7eJNRM2CU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; s=default; bh=ujpyZyQHp vRkt/GnlLVcG9wB4bA=; b=CJiupZG96OOGDuT+k9uQwTC2woF98KjVl2TQXQNp/ SePA9fsv+tIrF/jSle284dDaOG5l+vhOT/RXXnUb7pJwvbxzSK9Dfc9HlmuFGgW3 WPpuOubWo68sgE07oBgYCnNIjtIpFb+vnBdY9OF0DEAgu68Zww+b1CjBRrproZVk zM= Received: (qmail 18721 invoked by alias); 24 May 2016 14:28:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 18711 invoked by uid 89); 24 May 2016 14:28:14 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.3 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=acquiring, $25, 35802, emulation X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 24 May 2016 14:28:04 +0000 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Websense Email with ESMTPS id B1AEB34D477DC; Tue, 24 May 2016 15:27:57 +0100 (IST) Received: from hhmail02.hh.imgtec.org ([fe80::5400:d33e:81a4:f775]) by HHMAIL01.hh.imgtec.org ([fe80::710b:f219:72bc:e0b3%26]) with mapi id 14.03.0266.001; Tue, 24 May 2016 15:28:01 +0100 From: Robert Suchanek To: Matthew Fortune , "Catherine_Moore@mentor.com" CC: Simon Dardis , "gcc-patches@gcc.gnu.org" Subject: [PATCH][MIPS] Remove "new" MIPS TLS access patterns Date: Tue, 24 May 2016 14:28:00 +0000 Message-ID: MIME-Version: 1.0 X-IsSubscribed: yes Hi, The below finishes the revert of r137670 that was already partially reverted in r137734 as part of PR target/35802. It would appear that the revert was not completed because of a spill failure at the time. As LRA can handle the 'v' constraint just fine and MIPS is going to drop the support for the classic reload, there is no need for this workaround that introduces spurious moves hurting the performance. No regression. Ok to commit? Regards, Robert 2016-05-24 Simon Dardis gcc/ * config/mips/constraints.md (V1_REG): Update comment. * config/mips/mips.md (get_tls_get_tp_): Remove. (*get_tls_tp_): Rename. * doc/md.texi: Update the MIPS "v" constraint. --- gcc/config/mips/constraints.md | 6 +++--- gcc/config/mips/mips.md | 26 +++----------------------- gcc/doc/md.texi | 3 +-- 3 files changed, 7 insertions(+), 28 deletions(-) diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md index 56b363e..155b212 100644 --- a/gcc/config/mips/constraints.md +++ b/gcc/config/mips/constraints.md @@ -60,11 +60,11 @@ (define_register_constraint "e" "LEA_REGS" (define_register_constraint "j" "PIC_FN_ADDR_REG" "@internal") +;; FIXME: Remove this comment and below once the MIPS backend can +;; only be used with LRA. ;; Don't use this constraint in gcc code! It runs the risk of ;; introducing a spill failure; see tls_get_tp_. -(define_register_constraint "v" "V1_REG" - "Register @code{$3}. Do not use this constraint in new code; - it is retained only for compatibility with glibc.") +(define_register_constraint "v" "V1_REG" "@internal") (define_register_constraint "y" "GR_REGS" "Equivalent to @code{r}; retained for backwards compatibility.") diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 527f2e1..432ab1a 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -7386,29 +7386,9 @@ (define_insn "*mips16e_save_restore" ;; MIPS 32r2 specification, but we use it on any architecture because ;; we expect it to be emulated. Use .set to force the assembler to ;; accept it. -;; -;; We do not use a constraint to force the destination to be $3 -;; because $3 can appear explicitly as a function return value. -;; If we leave the use of $3 implicit in the constraints until -;; reload, we may end up making a $3 return value live across -;; the instruction, leading to a spill failure when reloading it. -(define_insn_and_split "tls_get_tp_" - [(set (match_operand:P 0 "register_operand" "=d") - (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP)) - (clobber (reg:P TLS_GET_TP_REGNUM))] - "HAVE_AS_TLS && !TARGET_MIPS16" - "#" - "&& reload_completed" - [(set (reg:P TLS_GET_TP_REGNUM) - (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP)) - (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))] - "" - [(set_attr "type" "unknown") - (set_attr "mode" "") - (set_attr "insn_count" "2")]) -(define_insn "*tls_get_tp__split" - [(set (reg:P TLS_GET_TP_REGNUM) +(define_insn "tls_get_tp_" + [(set (match_operand:P 0 "register_operand" "=v") (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))] "HAVE_AS_TLS && !TARGET_MIPS16" { @@ -7418,7 +7398,7 @@ (define_insn "*tls_get_tp__split" return ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"; } [(set_attr "type" "unknown") - ; Since rdhwr always generates a trap for now, putting it in a delay + ; Since rdhwr may generate a trap, putting it in a delay ; slot would make the kernel's emulation of it much slower. (set_attr "can_delay" "no") (set_attr "mode" "")]) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index f2360c8..d1c88d2 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -2705,8 +2705,7 @@ A register suitable for use in an indirect jump. This will always be @code{$25} for @option{-mabicalls}. @item v -Register @code{$3}. Do not use this constraint in new code; -it is retained only for compatibility with glibc. +Register @code{$3}. The register for acquiring the TLS pointer. @item y Equivalent to @code{r}; retained for backwards compatibility.