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Shouldn't cortex-a15 enable ARM_FEATURE_EL2?

Message ID BLUPR0301MB203455969C9F25DB4CCD43849E740@BLUPR0301MB2034.namprd03.prod.outlook.com
State New
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Commit Message

Andrew Baumann May 13, 2016, 4:41 p.m. UTC 
Hi Peter,

I'm trying to use the MRS/MSR banked register instructions you recently implemented, but found that they raised an undefined instruction exception on the cortex-a15 CPU model. This seems to be caused by the check in msr_banked_access_decode(), which looks for ARM_FEATURE_V8 or ARM_FEATURE_EL2.

The quick kludge below worked for me, but I don't have high confidence in its correctness -- the CPU supports the virtualisation extensions, but I've no idea whether the rest of qemu is consistent with enabling that feature. I guess you have a better idea?


Cheers,
Andrew

Comments

Peter Maydell May 13, 2016, 4:56 p.m. UTC | #1 
On 13 May 2016 at 17:41, Andrew Baumann <Andrew.Baumann@microsoft.com> wrote:
> I'm trying to use the MRS/MSR banked register instructions you
> recently implemented, but found that they raised an undefined
> instruction exception on the cortex-a15 CPU model. This seems to
> be caused by the check in msr_banked_access_decode(), which looks
> for ARM_FEATURE_V8 or ARM_FEATURE_EL2.
>
> The quick kludge below worked for me, but I don't have high
> confidence in its correctness -- the CPU supports the virtualisation
>  extensions, but I've no idea whether the rest of qemu is consistent
> with enabling that feature. I guess you have a better idea?

Yeah, this came up earlier this week in the context of the A53
and A57:
 https://lists.nongnu.org/archive/html/qemu-devel/2016-05/msg01006.html

The short answer is that EL2 support isn't finished yet, and
I don't want to enable the feature until we have something that's
complete enough to be able to run a real guest that uses it.

thanks
-- PMM
diff mbox

Patch

--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -1132,6 +1132,7 @@  static void cortex_a15_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_LPAE);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
     cpu->midr = 0x412fc0f1;