diff mbox

[U-Boot,v2,06/18] net: macb: Flush correct cache portion when sending

Message ID 1462454902-6093-7-git-send-email-sjg@chromium.org
State Awaiting Upstream
Delegated to: Andreas Bießmann
Headers show

Commit Message

Simon Glass May 5, 2016, 1:28 p.m. UTC 
The end address of the cache flush must be cache-line-aligned since
otherwise (at least on ARM926-EJS) the request is ignored. When the cache
is enabled this means that packets are not sent.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---

Changes in v2: None

 drivers/net/macb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Andreas Bießmann May 28, 2016, 12:35 p.m. UTC | #1 
On 05.05.16 15:28, Simon Glass wrote:
> The end address of the cache flush must be cache-line-aligned since
> otherwise (at least on ARM926-EJS) the request is ignored. When the cache
> is enabled this means that packets are not sent.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Heiko Schocher <hs@denx.de>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

> ---
> 
> Changes in v2: None
> 
>  drivers/net/macb.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> index f0af40c..ecdfc1b 100644
> --- a/drivers/net/macb.c
> +++ b/drivers/net/macb.c
> @@ -280,7 +280,7 @@ static int _macb_send(struct macb_device *macb, const char *name, void *packet,
>  	barrier();
>  	macb_flush_ring_desc(macb, TX);
>  	/* Do we need check paddr and length is dcache line aligned? */
> -	flush_dcache_range(paddr, paddr + length);
> +	flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
>  	macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
>  
>  	/*
>
Andreas Bießmann June 12, 2016, 10:01 p.m. UTC | #2 
Dear Simon Glass,

Simon Glass <sjg@chromium.org> writes:
>The end address of the cache flush must be cache-line-aligned since
>otherwise (at least on ARM926-EJS) the request is ignored. When the cache
>is enabled this means that packets are not sent.
>
>Signed-off-by: Simon Glass <sjg@chromium.org>
>Reviewed-by: Heiko Schocher <hs@denx.de>
>Acked-by: Joe Hershberger <joe.hershberger@ni.com>
>Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
>---
>
>Changes in v2: None
>
> drivers/net/macb.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)

applied to u-boot-atmel/master, thanks!

Best regards,
Andreas Bießmann
diff mbox

Patch

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index f0af40c..ecdfc1b 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -280,7 +280,7 @@  static int _macb_send(struct macb_device *macb, const char *name, void *packet,
 	barrier();
 	macb_flush_ring_desc(macb, TX);
 	/* Do we need check paddr and length is dcache line aligned? */
-	flush_dcache_range(paddr, paddr + length);
+	flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
 	macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
 
 	/*