| Message ID | 20160321140016.GA58060@msticlxl57.ims.intel.com |
|---|---|
| State | New |
| Headers | show |
On Mon, 21 Mar 2016, Kirill Yukhin wrote: > Hello, > 1s in mask in i386.c/builtin_description enables > built-ins for corresponding bits. > So, actually if there're 2 1s in it - any bit set > enables built-in. > > AVX-512VL exploits mask in opposite way. > E.g.: > { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddqu > hi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_UHI }, > > This means that built-in enabled if *both* bits are set to 1. > > So, I've added special handling for OPTION_MASK_ISA_AVX512VL > into i386.c/def_builtin. > > Bootstrapped and regtested. > > Richard, > is it ok for main trunk? I defer to Uros. Richard. > > PR target/70325 > gcc/ > * config/i386/i386.c (def_builtin): Handle > OPTION_MASK_ISA_AVX512VL to be and-ed with other > bits. > gcc/testsuite/ > * gcc.target/i386/pr70325.c: New test. > > -- > Thanks, K > > commit 68c7dd92daad8d4365d0dcd3b1aa4c3ba2658660 > Author: Kirill Yukhin <kirill.yukhin@intel.com> > Date: Mon Mar 21 14:28:58 2016 +0300 > > AVX-512. Fix PR70325. > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c > index 3d8dbc4..9df5055 100644 > --- a/gcc/config/i386/i386.c > +++ b/gcc/config/i386/i386.c > @@ -32429,6 +32429,9 @@ def_builtin (HOST_WIDE_INT mask, const char *name, > { > ix86_builtins_isa[(int) code].isa = mask; > > + if (mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL) > + mask &= ~OPTION_MASK_ISA_AVX512VL; > + > mask &= ~OPTION_MASK_ISA_64BIT; > if (mask == 0 > || (mask & ix86_isa_flags) != 0 > diff --git a/gcc/testsuite/gcc.target/i386/pr70325.c b/gcc/testsuite/gcc.target/i386/pr70325.c > new file mode 100644 > index 0000000..e2b9342 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr70325.c > @@ -0,0 +1,12 @@ > +/* PR target/70325 */ > +/* { dg-do compile } */ > +/* { dg-options "-mavx512vl -O2" } */ > + > +typedef char C __attribute((__vector_size__(32))); > +typedef int I __attribute((__vector_size__(32))); > + > +void > +f(int a,I b) > +{ > + __builtin_ia32_storedquqi256_mask((C*)f,(C)b,a); /* { dg-warning "implicit declaration of function" } */ > +} > >
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 3d8dbc4..9df5055 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -32429,6 +32429,9 @@ def_builtin (HOST_WIDE_INT mask, const char *name, { ix86_builtins_isa[(int) code].isa = mask; + if (mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL) + mask &= ~OPTION_MASK_ISA_AVX512VL; + mask &= ~OPTION_MASK_ISA_64BIT; if (mask == 0 || (mask & ix86_isa_flags) != 0 diff --git a/gcc/testsuite/gcc.target/i386/pr70325.c b/gcc/testsuite/gcc.target/i386/pr70325.c new file mode 100644 index 0000000..e2b9342 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr70325.c @@ -0,0 +1,12 @@ +/* PR target/70325 */ +/* { dg-do compile } */ +/* { dg-options "-mavx512vl -O2" } */ + +typedef char C __attribute((__vector_size__(32))); +typedef int I __attribute((__vector_size__(32))); + +void +f(int a,I b) +{ + __builtin_ia32_storedquqi256_mask((C*)f,(C)b,a); /* { dg-warning "implicit declaration of function" } */ +}
Hello, 1s in mask in i386.c/builtin_description enables built-ins for corresponding bits. So, actually if there're 2 1s in it - any bit set enables built-in. AVX-512VL exploits mask in opposite way. E.g.: { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddqu hi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_UHI }, This means that built-in enabled if *both* bits are set to 1. So, I've added special handling for OPTION_MASK_ISA_AVX512VL into i386.c/def_builtin. Bootstrapped and regtested. Richard, is it ok for main trunk? PR target/70325 gcc/ * config/i386/i386.c (def_builtin): Handle OPTION_MASK_ISA_AVX512VL to be and-ed with other bits. gcc/testsuite/ * gcc.target/i386/pr70325.c: New test. -- Thanks, K commit 68c7dd92daad8d4365d0dcd3b1aa4c3ba2658660 Author: Kirill Yukhin <kirill.yukhin@intel.com> Date: Mon Mar 21 14:28:58 2016 +0300 AVX-512. Fix PR70325.