From patchwork Mon Mar 21 14:00:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Yukhin X-Patchwork-Id: 600134 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qTHYl2QWMz9s2Q for ; Tue, 22 Mar 2016 01:01:30 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=Ylxkto1s; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; q=dns; s=default; b=HHjs8Q+BS0cDeThstcFVQk6/6iVUX2dbsY4lAZaMX2jO4gFi5t flZg+zjv87bCOwjHRRISIrUKZs1NJfZDnKFYbWv+HGVg8HFE644aEiG06oKpPs8p /94W8VHvNNZCnyxgotNUoiMmUZYUcODMwTSgOyGLEE/Fn7nDXgT2zTrWE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; s= default; bh=lOMEwzl5HULfhQZvMCd/s+7SP+g=; b=Ylxkto1sFzlsrubXNe+N j7AdEO0g+nN4t6UGV3ckCdIjMnIzWQW30IDTW+QHfWESK7pAdaqwnSXlErgEUn6+ z3DoFsMHa6X7jYT6xQN+zWzjuWWDEUusrSlVlCtxbo8IHFNXBgFG8WA6SZ0FYwfa Bt95biFJrsPQrEYi/R0HIGM= Received: (qmail 67216 invoked by alias); 21 Mar 2016 14:01:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 67198 invoked by uid 89); 21 Mar 2016 14:01:19 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=UNKNOWN, ba X-HELO: mail-wm0-f49.google.com Received: from mail-wm0-f49.google.com (HELO mail-wm0-f49.google.com) (74.125.82.49) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Mon, 21 Mar 2016 14:01:09 +0000 Received: by mail-wm0-f49.google.com with SMTP id p65so152862825wmp.1 for ; Mon, 21 Mar 2016 07:01:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:mime-version :content-disposition:user-agent; bh=eBvoh3bLcPHYhMgi1qUuIg6BkvNroiTXSyD9BmMdSTo=; b=aJlKEbPeVm6HbWyH8awHC3g6T1mpQ2oXIM793h2zT9Qii8QqDWDlCwUHJZQm/HrRll BXaiepe0Y2SId8qEuLAiPSuA/R61J87dOIlXp3/RsZRGtQu4IG3bkktsFyH3YiIpP5FX 2JmtW+7a6YQE8yk5Q0AzAwAVWVKpRJz3aQtQvMjBP2h8bj2uVWbNIHQ6Yv4oUyKu3jQE xq5FkSWVDFBMwGvldeLMcyMkSA7KFE2h2MoM4nq0MEpbXYuHEZmLirjH84BamZuG9vBX dsdi59OAP/vXnBSmnqZdF74h1MA4Wj3XoQ9j14eUfID+khFeseZ06jKNkBEwmmZxGZv+ Jhpw== X-Gm-Message-State: AD7BkJK+5/bN26hYH9mLQqcJsZhdnfWDOFTyu4sFLJyJVtG1LTU05t9Q2hn9uktVWCaT1g== X-Received: by 10.28.101.133 with SMTP id z127mr14532318wmb.84.1458568866973; Mon, 21 Mar 2016 07:01:06 -0700 (PDT) Received: from msticlxl57.ims.intel.com (irdmzpr01-ext.ir.intel.com. [192.198.151.36]) by smtp.gmail.com with ESMTPSA id a16sm12613172wmi.0.2016.03.21.07.01.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Mar 2016 07:01:06 -0700 (PDT) Date: Mon, 21 Mar 2016 17:00:18 +0300 From: Kirill Yukhin To: Richard Biener Cc: Uros Bizjak , GCC Patches Subject: [PATCH, i386, AVX-512] Fix PR target/70325. Message-ID: <20160321140016.GA58060@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.23 (2014-03-12) X-IsSubscribed: yes Hello, 1s in mask in i386.c/builtin_description enables built-ins for corresponding bits. So, actually if there're 2 1s in it - any bit set enables built-in. AVX-512VL exploits mask in opposite way. E.g.: { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddqu hi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_UHI }, This means that built-in enabled if *both* bits are set to 1. So, I've added special handling for OPTION_MASK_ISA_AVX512VL into i386.c/def_builtin. Bootstrapped and regtested. Richard, is it ok for main trunk? PR target/70325 gcc/ * config/i386/i386.c (def_builtin): Handle OPTION_MASK_ISA_AVX512VL to be and-ed with other bits. gcc/testsuite/ * gcc.target/i386/pr70325.c: New test. --- Thanks, K commit 68c7dd92daad8d4365d0dcd3b1aa4c3ba2658660 Author: Kirill Yukhin Date: Mon Mar 21 14:28:58 2016 +0300 AVX-512. Fix PR70325. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 3d8dbc4..9df5055 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -32429,6 +32429,9 @@ def_builtin (HOST_WIDE_INT mask, const char *name, { ix86_builtins_isa[(int) code].isa = mask; + if (mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL) + mask &= ~OPTION_MASK_ISA_AVX512VL; + mask &= ~OPTION_MASK_ISA_64BIT; if (mask == 0 || (mask & ix86_isa_flags) != 0 diff --git a/gcc/testsuite/gcc.target/i386/pr70325.c b/gcc/testsuite/gcc.target/i386/pr70325.c new file mode 100644 index 0000000..e2b9342 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr70325.c @@ -0,0 +1,12 @@ +/* PR target/70325 */ +/* { dg-do compile } */ +/* { dg-options "-mavx512vl -O2" } */ + +typedef char C __attribute((__vector_size__(32))); +typedef int I __attribute((__vector_size__(32))); + +void +f(int a,I b) +{ + __builtin_ia32_storedquqi256_mask((C*)f,(C)b,a); /* { dg-warning "implicit declaration of function" } */ +}