| Message ID | 1457050214-117592-3-git-send-email-agraf@suse.de |
|---|---|
| State | Accepted |
| Delegated to: | Tom Rini |
| Headers | show |
On Fri, Mar 04, 2016 at 01:09:46AM +0100, Alexander Graf wrote: > When running in EL1, AArch64 knows two page table maps. One with addresses > that start with all zeros (TTBR0) and one with addresses that start with all > ones (TTBR1). > > In U-Boot we don't care about the high up maps, so just disable them to ensure > we don't walk an invalid page table by accident. > > Reported-by: Mark Rutland <mark.rutland@arm.com> > Signed-off-by: Alexander Graf <agraf@suse.de> Applied to u-boot/master, thanks!
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 9229532..d92f2d1 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -71,7 +71,7 @@ static u64 get_tcr(int el, u64 *pips, u64 *pva_bits) } if (el == 1) { - tcr = TCR_EL1_RSVD | (ips << 32); + tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE; } else if (el == 2) { tcr = TCR_EL2_RSVD | (ips << 16); } else { diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 39ff745..0080ae6 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -154,6 +154,7 @@ #define TCR_TG0_4K (0 << 14) #define TCR_TG0_64K (1 << 14) #define TCR_TG0_16K (2 << 14) +#define TCR_EPD1_DISABLE (1 << 23) #ifndef CONFIG_SYS_FULL_VA #define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */
When running in EL1, AArch64 knows two page table maps. One with addresses that start with all zeros (TTBR0) and one with addresses that start with all ones (TTBR1). In U-Boot we don't care about the high up maps, so just disable them to ensure we don't walk an invalid page table by accident. Reported-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Alexander Graf <agraf@suse.de> --- arch/arm/cpu/armv8/cache_v8.c | 2 +- arch/arm/include/asm/armv8/mmu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)