| Message ID | 1450580446-6435-6-git-send-email-marex@denx.de |
|---|---|
| State | Accepted |
| Delegated to: | Marek Vasut |
| Headers | show |
On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote: > Add common configuration bits for the Denali NAND controller and also > support for using it as a boot device in SPL. > > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com> > Cc: Chin Liang See <clsee@altera.com> > --- > include/configs/socfpga_common.h | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/include/configs/socfpga_common.h > b/include/configs/socfpga_common.h > index 4124d8b..8886ccf 100644 > --- a/include/configs/socfpga_common.h > +++ b/include/configs/socfpga_common.h > @@ -162,6 +162,19 @@ > #endif > > /* > + * NAND Support > + */ > +#ifdef CONFIG_NAND_DENALI > +#define CONFIG_SYS_MAX_NAND_DEVICE 1 > +#define CONFIG_SYS_NAND_MAX_CHIPS 1 > +#define CONFIG_SYS_NAND_ONFI_DETECTION > +#define CONFIG_NAND_DENALI_ECC_SIZE 512 > +#define CONFIG_SYS_NAND_REGS_BASE 0xffb80000 > +#define CONFIG_SYS_NAND_DATA_BASE 0xff900000 You can use SOCFPGA_NANDDATA_ADDRESS and SOCFPGA_NANDREGS_ADDRESS > +#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BA > SE + 0x10) > +#endif > + > +/* > * I2C support > */ > #define CONFIG_SYS_I2C > @@ -302,6 +315,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void); > #ifdef CONFIG_DM_SPI > #define CONFIG_SPL_SPI_SUPPORT > #endif > +#ifdef CONFIG_SPL_NAND_DENALI > +#define CONFIG_SPL_NAND_SUPPORT > +#endif > > /* SPL SDMMC boot support */ > #ifdef CONFIG_SPL_MMC_SUPPORT > @@ -324,6 +340,13 @@ unsigned int > cm_get_qspi_controller_clk_hz(void); > #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 > #endif > > +/* SPL NAND boot support */ > +#ifdef CONFIG_SPL_NAND_SUPPORT > +#define CONFIG_SYS_NAND_USE_FLASH_BBT > +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 I believe this is need for U-Boot too, right? Thanks Chin Liang > +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 > +#endif > + > /* > * Stack setup > */
On Tuesday, December 22, 2015 at 04:17:23 PM, Chin Liang See wrote: > On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote: > > Add common configuration bits for the Denali NAND controller and also > > support for using it as a boot device in SPL. > > > > Signed-off-by: Marek Vasut <marex@denx.de> > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com> > > Cc: Chin Liang See <clsee@altera.com> > > --- > > > > include/configs/socfpga_common.h | 23 +++++++++++++++++++++++ > > 1 file changed, 23 insertions(+) > > > > diff --git a/include/configs/socfpga_common.h > > b/include/configs/socfpga_common.h > > index 4124d8b..8886ccf 100644 > > --- a/include/configs/socfpga_common.h > > +++ b/include/configs/socfpga_common.h > > @@ -162,6 +162,19 @@ > > > > #endif > > > > /* > > > > + * NAND Support > > + */ > > +#ifdef CONFIG_NAND_DENALI > > +#define CONFIG_SYS_MAX_NAND_DEVICE 1 > > +#define CONFIG_SYS_NAND_MAX_CHIPS 1 > > +#define CONFIG_SYS_NAND_ONFI_DETECTION > > +#define CONFIG_NAND_DENALI_ECC_SIZE 512 > > +#define CONFIG_SYS_NAND_REGS_BASE 0xffb80000 > > +#define CONFIG_SYS_NAND_DATA_BASE 0xff900000 > > You can use SOCFPGA_NANDDATA_ADDRESS and SOCFPGA_NANDREGS_ADDRESS I would like to nuke these two altogether ;-) But they are not as critical as the USB, so OK. > > +#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BA > > SE + 0x10) > > +#endif > > + > > +/* > > > > * I2C support > > */ > > > > #define CONFIG_SYS_I2C > > > > @@ -302,6 +315,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void); > > > > #ifdef CONFIG_DM_SPI > > #define CONFIG_SPL_SPI_SUPPORT > > #endif > > > > +#ifdef CONFIG_SPL_NAND_DENALI > > +#define CONFIG_SPL_NAND_SUPPORT > > +#endif > > > > /* SPL SDMMC boot support */ > > #ifdef CONFIG_SPL_MMC_SUPPORT > > > > @@ -324,6 +340,13 @@ unsigned int > > cm_get_qspi_controller_clk_hz(void); > > > > #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 > > #endif > > > > +/* SPL NAND boot support */ > > +#ifdef CONFIG_SPL_NAND_SUPPORT > > +#define CONFIG_SYS_NAND_USE_FLASH_BBT > > +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 > > I believe this is need for U-Boot too, right? It's only needed for the SPL, I double-checked.
On Tuesday, December 22, 2015 at 04:17:23 PM, Chin Liang See wrote: > On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote: > > Add common configuration bits for the Denali NAND controller and also > > support for using it as a boot device in SPL. > > > > Signed-off-by: Marek Vasut <marex@denx.de> > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com> > > Cc: Chin Liang See <clsee@altera.com> > > --- > > > > include/configs/socfpga_common.h | 23 +++++++++++++++++++++++ > > 1 file changed, 23 insertions(+) > > > > diff --git a/include/configs/socfpga_common.h > > b/include/configs/socfpga_common.h > > index 4124d8b..8886ccf 100644 > > --- a/include/configs/socfpga_common.h > > +++ b/include/configs/socfpga_common.h > > @@ -162,6 +162,19 @@ > > > > #endif > > > > /* > > > > + * NAND Support > > + */ > > +#ifdef CONFIG_NAND_DENALI > > +#define CONFIG_SYS_MAX_NAND_DEVICE 1 > > +#define CONFIG_SYS_NAND_MAX_CHIPS 1 > > +#define CONFIG_SYS_NAND_ONFI_DETECTION > > +#define CONFIG_NAND_DENALI_ECC_SIZE 512 > > +#define CONFIG_SYS_NAND_REGS_BASE 0xffb80000 > > +#define CONFIG_SYS_NAND_DATA_BASE 0xff900000 > > You can use SOCFPGA_NANDDATA_ADDRESS and SOCFPGA_NANDREGS_ADDRESS Fixed and applied, thanks. I believe we should be getting close to a good stable setup, so it's about time to start testing once I issue this last heftier PR. Best regards, Marek Vasut
On Tue, 2015-12-22 at 21:23 +0100, Marek Vasut wrote: > On Tuesday, December 22, 2015 at 04:17:23 PM, Chin Liang See wrote: > > On Sun, 2015-12-20 at 04:00 +0100, Marek Vasut wrote: > > > Add common configuration bits for the Denali NAND controller and > > > also > > > support for using it as a boot device in SPL. > > > > > > Signed-off-by: Marek Vasut <marex@denx.de> > > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com> > > > Cc: Chin Liang See <clsee@altera.com> > > > --- > > > > > > include/configs/socfpga_common.h | 23 +++++++++++++++++++++++ > > > 1 file changed, 23 insertions(+) > > > > > > diff --git a/include/configs/socfpga_common.h > > > b/include/configs/socfpga_common.h > > > index 4124d8b..8886ccf 100644 > > > --- a/include/configs/socfpga_common.h > > > +++ b/include/configs/socfpga_common.h > > > @@ -162,6 +162,19 @@ > > > > > > #endif > > > > > > /* > > > > > > + * NAND Support > > > + */ > > > +#ifdef CONFIG_NAND_DENALI > > > +#define CONFIG_SYS_MAX_NAND_DEVICE 1 > > > +#define CONFIG_SYS_NAND_MAX_CHIPS 1 > > > +#define CONFIG_SYS_NAND_ONFI_DETECTION > > > +#define CONFIG_NAND_DENALI_ECC_SIZE 512 > > > +#define CONFIG_SYS_NAND_REGS_BASE 0xffb80000 > > > +#define CONFIG_SYS_NAND_DATA_BASE 0xff900000 > > > > You can use SOCFPGA_NANDDATA_ADDRESS and SOCFPGA_NANDREGS_ADDRESS > > Fixed and applied, thanks. Nice Thanks Chin Liang > > I believe we should be getting close to a good stable setup, so it's > about > time to start testing once I issue this last heftier PR. > > Best regards, > Marek Vasut
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 4124d8b..8886ccf 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -162,6 +162,19 @@ #endif /* + * NAND Support + */ +#ifdef CONFIG_NAND_DENALI +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_DENALI_ECC_SIZE 512 +#define CONFIG_SYS_NAND_REGS_BASE 0xffb80000 +#define CONFIG_SYS_NAND_DATA_BASE 0xff900000 +#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) +#endif + +/* * I2C support */ #define CONFIG_SYS_I2C @@ -302,6 +315,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #ifdef CONFIG_DM_SPI #define CONFIG_SPL_SPI_SUPPORT #endif +#ifdef CONFIG_SPL_NAND_DENALI +#define CONFIG_SPL_NAND_SUPPORT +#endif /* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT @@ -324,6 +340,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 #endif +/* SPL NAND boot support */ +#ifdef CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#endif + /* * Stack setup */
Add common configuration bits for the Denali NAND controller and also support for using it as a boot device in SPL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> --- include/configs/socfpga_common.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)