diff mbox

[U-Boot,6/8] net: zynq: Fix mdc clock division setting for 100Mbit/s

Message ID 6fe65d93a2ff6a06a0e0a0aedb198ca959ec5c61.1445959075.git.michal.simek@xilinx.com
State Accepted
Delegated to: Michal Simek
Headers show

Commit Message

Michal Simek Oct. 27, 2015, 3:17 p.m. UTC 
Using set and clear macro is incorrect because it is not overwritting
origin mdc clock division setup.
For example origin setup is 8(0b001) and new setup is 64(0b100) which
means 0b101 is setup which is 96 divider.
Using writel to rewrite all setting like for 1000Mbit/s case.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 drivers/net/zynq_gem.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Joe Hershberger Nov. 2, 2015, 9:40 p.m. UTC | #1 
On Tue, Oct 27, 2015 at 10:17 AM, Michal Simek <michal.simek@xilinx.com> wrote:
> Using set and clear macro is incorrect because it is not overwritting
> origin mdc clock division setup.
> For example origin setup is 8(0b001) and new setup is 64(0b100) which
> means 0b101 is setup which is 96 divider.
> Using writel to rewrite all setting like for 1000Mbit/s case.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
diff mbox

Patch

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index c56e02132ae9..a9384ce73144 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -410,8 +410,8 @@  static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
 		clk_rate = ZYNQ_GEM_FREQUENCY_1000;
 		break;
 	case SPEED_100:
-		clrsetbits_le32(&regs->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
-				ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
+		writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100,
+		       &regs->nwcfg);
 		clk_rate = ZYNQ_GEM_FREQUENCY_100;
 		break;
 	case SPEED_10: