diff mbox

[U-Boot,1/3] armv8/mmu: Clean up TCR programming

Message ID 1440064335-25909-1-git-send-email-thierry.reding@gmail.com
State Accepted
Delegated to: Albert ARIBAUD
Headers show

Commit Message

Thierry Reding Aug. 20, 2015, 9:52 a.m. UTC 
From: Thierry Reding <treding@nvidia.com>

Use the inner shareable attribute for memory, which makes more sense
considering that this code is called when caches are being enabled.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm/include/asm/armv8/mmu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Albert ARIBAUD Oct. 15, 2015, 12:52 p.m. UTC | #1 
Hello Thierry,

On Thu, 20 Aug 2015 11:52:13 +0200, Thierry Reding
<thierry.reding@gmail.com> wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Use the inner shareable attribute for memory, which makes more sense
> considering that this code is called when caches are being enabled.
> 
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Signed-off-by: Thierry Reding <treding@nvidia.com>

Series applied to u-boot-arm/master as a bugfix.

Amicalement,
diff mbox

Patch

diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 04fa0be64ca3..6d42f5533a74 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -102,9 +102,9 @@ 
 #define TCR_EL2_IPS_BITS	(3 << 16)	/* 42 bits physical address */
 #define TCR_EL3_IPS_BITS	(3 << 16)	/* 42 bits physical address */
 
-/* PTWs cacheable, inner/outer WBWA and non-shareable */
+/* PTWs cacheable, inner/outer WBWA and inner shareable */
 #define TCR_FLAGS		(TCR_TG0_64K |		\
-				TCR_SHARED_NON |	\
+				TCR_SHARED_INNER |	\
 				TCR_ORGN_WBWA |		\
 				TCR_IRGN_WBWA |		\
 				TCR_T0SZ(VA_BITS))