diff mbox

[U-Boot,07/11] imx: mx6ul update soc related settings

Message ID 1435834988-13032-8-git-send-email-Peng.Fan@freescale.com
State Changes Requested
Delegated to: Stefano Babic
Headers show

Commit Message

Peng Fan July 2, 2015, 11:03 a.m. UTC 
Add MX6UL in Kconfig, default select SYS_L2CACHE_OFF.
update WDOG settings. No need to gate/ungate all PFDs for i.MX6UL.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
---
 arch/arm/cpu/armv7/mx6/Kconfig | 4 ++++
 arch/arm/cpu/armv7/mx6/soc.c   | 4 ++--
 2 files changed, 6 insertions(+), 2 deletions(-)

Comments

Fabio Estevam July 2, 2015, 2:12 p.m. UTC | #1 
Hi Peng,

On Thu, Jul 2, 2015 at 8:03 AM, Peng Fan <Peng.Fan@freescale.com> wrote:
> Add MX6UL in Kconfig, default select SYS_L2CACHE_OFF.

Could you tell us more about this? Why L2 cache needs to be disabled?

Regards,

Fabio Estevam
Marek Vasut July 2, 2015, 6:33 p.m. UTC | #2 
On Thursday, July 02, 2015 at 01:03:04 PM, Peng Fan wrote:
> Add MX6UL in Kconfig, default select SYS_L2CACHE_OFF.

Why ?

> update WDOG settings.

I'd put this into separate patch, since L2 cache and watchdog are
completely unrelated (and so is L2 cache and clock).

> No need to gate/ungate all PFDs for i.MX6UL.
> 
> Signed-off-by: Ye.Li <B37916@freescale.com>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

[...]

Best regards,
Marek Vasut
Peng Fan July 3, 2015, 1:36 a.m. UTC | #3 
Hi, Marek and Fabio

On Thu, Jul 02, 2015 at 08:33:34PM +0200, Marek Vasut wrote:
>On Thursday, July 02, 2015 at 01:03:04 PM, Peng Fan wrote:
>> Add MX6UL in Kconfig, default select SYS_L2CACHE_OFF.
>
>Why ?

i.MX6UL features an Cortex-A7 core, it does not have PL310. As we know
Cortex-A7 does not support L2 Cache open/close switch. When you enable
D-Cache, L2 Cache default enabled. I'll add more commit msg to explain
this.

>
>> update WDOG settings.
>
>I'd put this into separate patch, since L2 cache and watchdog are
>completely unrelated (and so is L2 cache and clock).

Will split this patch into small patches.

>
>> No need to gate/ungate all PFDs for i.MX6UL.
>> 
>> Signed-off-by: Ye.Li <B37916@freescale.com>
>> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
>
>[...]
>
>Best regards,
>Marek Vasut

Regards,
Peng.
Marek Vasut July 3, 2015, 1:39 p.m. UTC | #4 
On Friday, July 03, 2015 at 03:36:00 AM, Peng Fan wrote:
> Hi, Marek and Fabio

Hi,

> On Thu, Jul 02, 2015 at 08:33:34PM +0200, Marek Vasut wrote:
> >On Thursday, July 02, 2015 at 01:03:04 PM, Peng Fan wrote:
> >> Add MX6UL in Kconfig, default select SYS_L2CACHE_OFF.
> >
> >Why ?
> 
> i.MX6UL features an Cortex-A7 core, it does not have PL310. As we know
> Cortex-A7 does not support L2 Cache open/close switch. When you enable
> D-Cache, L2 Cache default enabled. I'll add more commit msg to explain
> this.

Thanks, now you wrote yourself a nice commit message ;-)

> >> update WDOG settings.
> >
> >I'd put this into separate patch, since L2 cache and watchdog are
> >completely unrelated (and so is L2 cache and clock).
> 
> Will split this patch into small patches.

Thanks!

Best regards,
Marek Vasut
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 10908c4..fceba27 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -25,6 +25,10 @@  config MX6SL
 config MX6SX
 	bool
 
+config MX6UL
+	select SYS_L2CACHE_OFF
+	bool
+
 choice
 	prompt "MX6 board select"
 	optional
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index e80c09c..20abe3f 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -317,7 +317,7 @@  static void imx_set_wdog_powerdown(bool enable)
 	struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
 	struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
 
-#ifdef CONFIG_MX6SX
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
 	struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
 	writew(enable, &wdog3->wmcr);
 #endif
@@ -530,7 +530,7 @@  void s_init(void)
 	u32 mask528;
 	u32 reg, periph1, periph2;
 
-	if (is_cpu_type(MXC_CPU_MX6SX))
+	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
 		return;
 
 	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs