diff mbox

[U-Boot] Marvell Armada XP SATA support

Message ID CAOrV_gD2zxb4jfiExHbTxj-n828=wgWHNLhOUXEsXCsgf1Az3Q@mail.gmail.com
State Superseded
Delegated to: Stefan Roese
Headers show

Commit Message

Anton Schubert June 30, 2015, 9:28 a.m. UTC 
That should be it. Although it's probably a good idea to do this in cpu.c
as you did with your a38x ahci support.
Thanks for your help.

Anton

---
 arch/arm/mach-mvebu/include/mach/soc.h |  1 +
 drivers/block/mvsata_ide.c             | 46
++++++++++++++++++++++++++++++++++
 include/configs/db-mv784mp-gp.h        | 29 +++++++++++++++++++++
 3 files changed, 76 insertions(+)

  * mv-common.h should be defined after CMD configs since it used them
  * to enable certain macros

Comments

Anton Schubert July 1, 2015, 10:20 a.m. UTC | #1 
Hi,

I figured out my problem was just ATA security. After unlocking the code
above works fine for MV78260.

Thanks,
 Anton

2015-06-30 11:28 GMT+02:00 Anton Schubert <anton.schubert@gmx.de>:

> That should be it. Although it's probably a good idea to do this in cpu.c
> as you did with your a38x ahci support.
> Thanks for your help.
>
> Anton
>
> ---
>  arch/arm/mach-mvebu/include/mach/soc.h |  1 +
>  drivers/block/mvsata_ide.c             | 46
> ++++++++++++++++++++++++++++++++++
>  include/configs/db-mv784mp-gp.h        | 29 +++++++++++++++++++++
>  3 files changed, 76 insertions(+)
>
> diff --git a/arch/arm/mach-mvebu/include/mach/soc.h
> b/arch/arm/mach-mvebu/include/mach/soc.h
> index 0a9307c..2a8234d 100644
> --- a/arch/arm/mach-mvebu/include/mach/soc.h
> +++ b/arch/arm/mach-mvebu/include/mach/soc.h
> @@ -51,6 +51,7 @@
>  #define MVEBU_REG_PCIE_BASE    (MVEBU_REGISTER(0x40000))
>  #define MVEBU_EGIGA0_BASE    (MVEBU_REGISTER(0x70000))
>  #define MVEBU_EGIGA1_BASE    (MVEBU_REGISTER(0x74000))
> +#define MVEBU_SATA_BASE    (MVEBU_REGISTER(0xA0000))
>
>  #define SDRAM_MAX_CS        4
>  #define SDRAM_ADDR_MASK        0xFF000000
> diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
> index e54d564..ace061a 100644
> --- a/drivers/block/mvsata_ide.c
> +++ b/drivers/block/mvsata_ide.c
> @@ -13,6 +13,8 @@
>  #include <asm/arch/orion5x.h>
>  #elif defined(CONFIG_KIRKWOOD)
>  #include <asm/arch/soc.h>
> +#elif defined(CONFIG_ARMADA_XP)
> +#include <linux/mbus.h>
>  #endif
>
>  /* SATA port registers */
> @@ -90,6 +92,46 @@ struct mvsata_port_registers {
>  #define MVSATA_STATUS_TIMEOUT    -1
>
>  /*
> + * Registers for SATA MBUS memory windows
> + */
> +
> +#define MVSATA_WIN_CONTROL(w)    (MVEBU_SATA_BASE + 0x30 + ((w) << 4))
> +#define MVSATA_WIN_BASE(w)    (MVEBU_SATA_BASE + 0x34 + ((w) << 4))
> +
> +/*
> + * Initialize SATA memory windows for Armada XP
> + */
> +
> +#ifdef CONFIG_ARMADA_XP
> +static void mvsata_ide_conf_mbus_windows(void)
> +{
> +    const struct mbus_dram_target_info *dram;
> +    int i;
> +
> +    dram = mvebu_mbus_dram_info();
> +
> +    /* Disable windows, Set Size/Base to 0  */
> +    for (i = 0; i < 4; i++) {
> +        writel(0, MVSATA_WIN_CONTROL(i));
> +        writel(0, MVSATA_WIN_BASE(i));
> +    }
> +
> +    for (i = 0; i < dram->num_cs; i++) {
> +        const struct mbus_dram_window *cs = dram->cs + i;
> +
> +        printf("%s: sata window %d\n", __func__, i);
> +        printf("%s: size %04x, attr %02x, target %01x\n", __func__,
> cs->size, cs->mbus_attr, dram->mbus_dram_target_id);
> +        printf("%s: base %04x\n\n", __func__, cs->base);
> +
> +        writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
> +                (dram->mbus_dram_target_id << 4) | 1,
> +                MVSATA_WIN_CONTROL(i));
> +        writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
> +    }
> +}
> +#endif
> +
> +/*
>   * Initialize one MVSATAHC port: set SControl's IPM to "always active"
>   * and DET to "reset", then wait for SStatus's DET to become "device and
>   * comm ok" (or time out after 50 us if no device), then set SControl's
> @@ -137,6 +179,10 @@ int ide_preinit(void)
>      int ret = MVSATA_STATUS_TIMEOUT;
>      int status;
>
> +#ifdef CONFIG_ARMADA_XP
> +    mvsata_ide_conf_mbus_windows();
> +#endif
> +
>      /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
>  #if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
>      status = mvsata_ide_initialize_port(
> diff --git a/include/configs/db-mv784mp-gp.h
> b/include/configs/db-mv784mp-gp.h
> index c33a588..299bc82 100644
> --- a/include/configs/db-mv784mp-gp.h
> +++ b/include/configs/db-mv784mp-gp.h
> @@ -32,6 +32,8 @@
>  #define CONFIG_CMD_SPI
>  #define CONFIG_CMD_TFTPPUT
>  #define CONFIG_CMD_TIME
> +#define CONFIG_CMD_BOOTZ
> +#define CONFIG_CMD_IDE
>
>  /* I2C */
>  #define CONFIG_SYS_I2C
> @@ -60,6 +62,33 @@
>  #define CONFIG_SYS_CONSOLE_INFO_QUIET    /* don't print console @ startup
> */
>  #define CONFIG_SYS_ALT_MEMTEST
>
> +/* IDE/ATA/SATA */
> +#ifdef CONFIG_CMD_IDE
> +#define __io
> +#define CONFIG_IDE_PREINIT
> +#define CONFIG_MVSATA_IDE
> +
> +/* Needs byte-swapping for ATA data register */
> +#define CONFIG_IDE_SWAP_IO
> +
> +#define CONFIG_SYS_ATA_REG_OFFSET    0x0100      /* Offset for normal
> register accesses*/
> +#define CONFIG_SYS_ATA_DATA_OFFSET    0x0100      /* Offset for data I/O
> */
> +#define CONFIG_SYS_ATA_ALT_OFFSET    0x0100      /* Offset for data I/O */
> +
> +/* Each 8-bit ATA register is aligned to a 4-bytes address */
> +#define CONFIG_SYS_ATA_STRIDE        4
> +
> +/* CONFIG_CMD_IDE requires some #defines for ATA registers */
> +#define CONFIG_SYS_IDE_MAXBUS          2
> +#define CONFIG_SYS_IDE_MAXDEVICE       2
> +
> +/* ATA registers base is at SATA controller base */
> +#define CONFIG_SYS_ATA_BASE_ADDR    MVEBU_SATA_BASE
> +#define CONFIG_SYS_ATA_IDE0_OFFSET    0x2000
> +
> +#define CONFIG_DOS_PARTITION
> +#endif /* CONFIG_CMD_IDE */
> +
>  /*
>   * mv-common.h should be defined after CMD configs since it used them
>   * to enable certain macros
> --
> 2.3.6
>
>
> 2015-06-30 8:57 GMT+02:00 Stefan Roese <sr@denx.de>:
>
>> Hi Anton,
>>
>> On 29.06.2015 19:01, Anton Schubert wrote:
>>
>>> 2015-06-23 14:38 GMT+02:00 Stefan Roese <sr@denx.de <mailto:sr@denx.de
>>> >>:
>>>
>>>     Hi Anton,
>>>
>>>     On 23.06.2015 13:23, Bin Meng wrote:
>>>
>>>         On Tue, Jun 23, 2015 at 5:35 PM, Anton Schubert
>>>         <anton.schubert@gmx.de <mailto:anton.schubert@gmx.de>> wrote
>>>
>>>
>>>
>>>             but noticed that there doesn't seem to be a driver for the
>>> SATA
>>>             controller.
>>>             Are there any plans to support SATA on Armada XP or is our
>>>             only option to
>>>             migrate the old driver?
>>>
>>>
>>>         Is the Marvell SATA controller AHCI compatible? If yes, U-Boot
>>>         has the
>>>         AHCI driver which should work.
>>>
>>>
>>>     No, the AXP SATA controller is unfortunately not AHCI compatible
>>>     (the A38x seems to be though). The mvsata driver
>>>     (drivers/block/mvsata_ide.c) might be a pretty good start for the
>>>     AXP though (I didn't check this closely).
>>>
>>>
>>> Hi,
>>> many thanks for your hints.
>>>
>>> I managed to get ide_ident working with mvsata_ide.c by setting the Sata
>>> address windows (using mbus.c analogous to the mvneta driver). But I'm
>>> kind of stuck now as ATA reads will just result in timeouts:
>>>
>>> ide_read dev 0 start 0, blocks 1 buffer at 7FBA9C60
>>> ide_outb (dev= 0, port= 0x118, val= 0xe0) : @ 0xf10a2118
>>> ide_inb (dev= 0, port= 0x11c) : @ 0xf10a211c -> 0x50
>>> ide_outb (dev= 0, port= 0x11c, val= 0xe5) : @ 0xf10a211c
>>> ide_inb (dev= 0, port= 0x11c) : @ 0xf10a211c -> 0x50
>>> ide_inb (dev= 0, port= 0x108) : @ 0xf10a2108 -> 0xff
>>> Powersaving FF
>>> ide_inb (dev= 0, port= 0x11c) : @ 0xf10a211c -> 0x50
>>> ide_outb (dev= 0, port= 0x108, val= 0x01) : @ 0xf10a2108
>>> ide_outb (dev= 0, port= 0x10c, val= 0x00) : @ 0xf10a210c
>>> ide_outb (dev= 0, port= 0x110, val= 0x00) : @ 0xf10a2110
>>> ide_outb (dev= 0, port= 0x114, val= 0x00) : @ 0xf10a2114
>>> ide_outb (dev= 0, port= 0x118, val= 0xe0) : @ 0xf10a2118
>>> ide_outb (dev= 0, port= 0x11c, val= 0x20) : @ 0xf10a211c
>>> ide_inb (dev= 0, port= 0x11c) : @ 0xf10a211c -> 0xd0
>>> ide_inb (dev= 0, port= 0x11c) : @ 0xf10a211c -> 0x51
>>> Error (no IRQ) dev 0 blk 0: status 0x51
>>>
>>>
>>> This is my current ide config:
>>> #define __io
>>> #define CONFIG_IDE_PREINIT
>>> #define CONFIG_MVSATA_IDE
>>>
>>> /* Needs byte-swapping for ATA data register */
>>> #define CONFIG_IDE_SWAP_IO
>>>
>>> #define CONFIG_SYS_ATA_REG_OFFSET        0x0100      /* Offset for
>>> normal register accesses*/
>>> #define CONFIG_SYS_ATA_DATA_OFFSET    0x0100      /* Offset for data I/O
>>> */
>>> #define CONFIG_SYS_ATA_ALT_OFFSET        0x0100      /* Offset for data
>>> I/O */
>>>
>>> /* Each 8-bit ATA register is aligned to a 4-bytes address */
>>> #define CONFIG_SYS_ATA_STRIDE        4
>>>
>>> /* CONFIG_CMD_IDE requires some #defines for ATA registers */
>>> #define CONFIG_SYS_IDE_MAXBUS          2
>>> #define CONFIG_SYS_IDE_MAXDEVICE       2
>>>
>>> /* ATA registers base is at SATA controller base */
>>> #define CONFIG_SYS_ATA_BASE_ADDR    MVEBU_SATA_BASE /* 0xA0000 */
>>> #define CONFIG_SYS_ATA_IDE0_OFFSET    0x2000
>>>
>>> #define CONFIG_DOS_PARTITION
>>>
>>> I would be grateful for any pointers.
>>>
>>
>> Just send me the missing code (mbus address window setup etc) and I'll
>> give it a try on my DB-MV784MP-GP board.
>>
>> Thanks,
>> Stefan
>>
>>
>
Stefan Roese July 1, 2015, 10:39 a.m. UTC | #2 
Hi Anton,

On 01.07.2015 12:20, Anton Schubert wrote:
> I figured out my problem was just ATA security. After unlocking the code
> above works fine for MV78260.

Great. Then please send a patch to the list to add support for SATA on AXP.

Thanks,
Stefan
Anton Schubert July 1, 2015, 1:41 p.m. UTC | #3 
Hi Stefan,

2015-07-01 12:39 GMT+02:00 Stefan Roese <sr@denx.de>:

> Hi Anton,
>
> On 01.07.2015 12:20, Anton Schubert wrote:
>
>> I figured out my problem was just ATA security. After unlocking the code
>> above works fine for MV78260.
>>
>
> Great. Then please send a patch to the list to add support for SATA on AXP.
>
> Thanks,
> Stefan
>
>
Should i move the mbus init code to mach-mvebu/cpu.c for that purpose?
Additionally, what would you recommend for the MVEBU_SATA_BASE define as it
would be ambiguous after the a38x patch.

Thanks,
Anton
Stefan Roese July 1, 2015, 2:55 p.m. UTC | #4 
Hi Anton,

On 01.07.2015 15:41, Anton Schubert wrote:
> 2015-07-01 12:39 GMT+02:00 Stefan Roese <sr@denx.de <mailto:sr@denx.de>>:
>
>     Hi Anton,
>
>     On 01.07.2015 12:20, Anton Schubert wrote:
>
>         I figured out my problem was just ATA security. After unlocking
>         the code
>         above works fine for MV78260.
>
>
>     Great. Then please send a patch to the list to add support for SATA
>     on AXP.
>
>     Thanks,
>     Stefan
>
>
> Should i move the mbus init code to mach-mvebu/cpu.c for that purpose?

No, please keep it in the driver. I only moved it into cpu.c since there 
is no MVEBU specific driver in the AHCI/SATA case.

> Additionally, what would you recommend for the MVEBU_SATA_BASE define as
> it would be ambiguous after the a38x patch.

Why not just use the same name/macro?

Thanks,
Stefan
Anton Schubert July 1, 2015, 3:09 p.m. UTC | #5 
Hi Stefan,

2015-07-01 16:55 GMT+02:00 Stefan Roese <sr@denx.de>:

> Hi Anton,
>
> On 01.07.2015 15:41, Anton Schubert wrote:
>
>> 2015-07-01 12:39 GMT+02:00 Stefan Roese <sr@denx.de <mailto:sr@denx.de>>:
>>
>>     Hi Anton,
>>
>>     On 01.07.2015 12:20, Anton Schubert wrote:
>>
>>         I figured out my problem was just ATA security. After unlocking
>>         the code
>>         above works fine for MV78260.
>>
>>
>>     Great. Then please send a patch to the list to add support for SATA
>>     on AXP.
>>
>>     Thanks,
>>     Stefan
>>
>>
>> Should i move the mbus init code to mach-mvebu/cpu.c for that purpose?
>>
>
> No, please keep it in the driver. I only moved it into cpu.c since there
> is no MVEBU specific driver in the AHCI/SATA case.
>
>  Additionally, what would you recommend for the MVEBU_SATA_BASE define as
>> it would be ambiguous after the a38x patch.
>>
>
> Why not just use the same name/macro?
>

I think it would be a bit confusing with MVEBU_SATA0_BASE for A38X and
MVEBU_SATA_BASE for AXP in the same header. (As I don't have access to the
A38X Spec I don't know how similar they really are)

Anton
Stefan Roese July 1, 2015, 3:19 p.m. UTC | #6 
Hi Anton,

On 01.07.2015 17:09, Anton Schubert wrote:
>         Additionally, what would you recommend for the MVEBU_SATA_BASE
>         define as
>         it would be ambiguous after the a38x patch.
>
>
>     Why not just use the same name/macro?
>
> I think it would be a bit confusing with MVEBU_SATA0_BASE for A38X and
> MVEBU_SATA_BASE for AXP in the same header. (As I don't have access to
> the A38X Spec I don't know how similar they really are)

Do the addresses differ? If not, then please use the same macro and 
perhaps add a comment, that on AXP this is not AHCI compatible. And on 
A38x it is.

If the addresses differ, I suggest to use a name like:

MVEBU_AXP_SATA_BASE

Thanks,
Stefan
diff mbox

Patch

diff --git a/arch/arm/mach-mvebu/include/mach/soc.h
b/arch/arm/mach-mvebu/include/mach/soc.h
index 0a9307c..2a8234d 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -51,6 +51,7 @@ 
 #define MVEBU_REG_PCIE_BASE    (MVEBU_REGISTER(0x40000))
 #define MVEBU_EGIGA0_BASE    (MVEBU_REGISTER(0x70000))
 #define MVEBU_EGIGA1_BASE    (MVEBU_REGISTER(0x74000))
+#define MVEBU_SATA_BASE    (MVEBU_REGISTER(0xA0000))

 #define SDRAM_MAX_CS        4
 #define SDRAM_ADDR_MASK        0xFF000000
diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c
index e54d564..ace061a 100644
--- a/drivers/block/mvsata_ide.c
+++ b/drivers/block/mvsata_ide.c
@@ -13,6 +13,8 @@ 
 #include <asm/arch/orion5x.h>
 #elif defined(CONFIG_KIRKWOOD)
 #include <asm/arch/soc.h>
+#elif defined(CONFIG_ARMADA_XP)
+#include <linux/mbus.h>
 #endif

 /* SATA port registers */
@@ -90,6 +92,46 @@  struct mvsata_port_registers {
 #define MVSATA_STATUS_TIMEOUT    -1

 /*
+ * Registers for SATA MBUS memory windows
+ */
+
+#define MVSATA_WIN_CONTROL(w)    (MVEBU_SATA_BASE + 0x30 + ((w) << 4))
+#define MVSATA_WIN_BASE(w)    (MVEBU_SATA_BASE + 0x34 + ((w) << 4))
+
+/*
+ * Initialize SATA memory windows for Armada XP
+ */
+
+#ifdef CONFIG_ARMADA_XP
+static void mvsata_ide_conf_mbus_windows(void)
+{
+    const struct mbus_dram_target_info *dram;
+    int i;
+
+    dram = mvebu_mbus_dram_info();
+
+    /* Disable windows, Set Size/Base to 0  */
+    for (i = 0; i < 4; i++) {
+        writel(0, MVSATA_WIN_CONTROL(i));
+        writel(0, MVSATA_WIN_BASE(i));
+    }
+
+    for (i = 0; i < dram->num_cs; i++) {
+        const struct mbus_dram_window *cs = dram->cs + i;
+
+        printf("%s: sata window %d\n", __func__, i);
+        printf("%s: size %04x, attr %02x, target %01x\n", __func__,
cs->size, cs->mbus_attr, dram->mbus_dram_target_id);
+        printf("%s: base %04x\n\n", __func__, cs->base);
+
+        writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
+                (dram->mbus_dram_target_id << 4) | 1,
+                MVSATA_WIN_CONTROL(i));
+        writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
+    }
+}
+#endif
+
+/*
  * Initialize one MVSATAHC port: set SControl's IPM to "always active"
  * and DET to "reset", then wait for SStatus's DET to become "device and
  * comm ok" (or time out after 50 us if no device), then set SControl's
@@ -137,6 +179,10 @@  int ide_preinit(void)
     int ret = MVSATA_STATUS_TIMEOUT;
     int status;

+#ifdef CONFIG_ARMADA_XP
+    mvsata_ide_conf_mbus_windows();
+#endif
+
     /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
 #if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
     status = mvsata_ide_initialize_port(
diff --git a/include/configs/db-mv784mp-gp.h
b/include/configs/db-mv784mp-gp.h
index c33a588..299bc82 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -32,6 +32,8 @@ 
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_TFTPPUT
 #define CONFIG_CMD_TIME
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_IDE

 /* I2C */
 #define CONFIG_SYS_I2C
@@ -60,6 +62,33 @@ 
 #define CONFIG_SYS_CONSOLE_INFO_QUIET    /* don't print console @ startup
*/
 #define CONFIG_SYS_ALT_MEMTEST

+/* IDE/ATA/SATA */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE
+
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+
+#define CONFIG_SYS_ATA_REG_OFFSET    0x0100      /* Offset for normal
register accesses*/
+#define CONFIG_SYS_ATA_DATA_OFFSET    0x0100      /* Offset for data I/O */
+#define CONFIG_SYS_ATA_ALT_OFFSET    0x0100      /* Offset for data I/O */
+
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE        4
+
+/* CONFIG_CMD_IDE requires some #defines for ATA registers */
+#define CONFIG_SYS_IDE_MAXBUS          2
+#define CONFIG_SYS_IDE_MAXDEVICE       2
+
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR    MVEBU_SATA_BASE
+#define CONFIG_SYS_ATA_IDE0_OFFSET    0x2000
+
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_CMD_IDE */
+
 /*