| Message ID | 1433923603-28119-2-git-send-email-Peng.Fan@freescale.com |
|---|---|
| State | Changes Requested |
| Headers | show |
Hi Peng, On 10/06/2015 10:06, Peng Fan wrote: > Add new cpu type for i.MX6DQP and providing a dynamical > detecting function. > > Signed-off-by: Peng Fan <Peng.Fan@freescale.com> > Signed-off-by: Ye.Li <B37916@freescale.com> > --- > arch/arm/cpu/armv7/mx6/soc.c | 4 +++- > arch/arm/include/asm/arch-mx6/imx-regs.h | 1 + > arch/arm/include/asm/arch-mx6/sys_proto.h | 6 ++++++ > 3 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c > index b21bd03..29de624 100644 > --- a/arch/arm/cpu/armv7/mx6/soc.c > +++ b/arch/arm/cpu/armv7/mx6/soc.c > @@ -62,6 +62,7 @@ u32 get_cpu_rev(void) > struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; > u32 reg = readl(&anatop->digprog_sololite); > u32 type = ((reg >> 16) & 0xff); > + u32 major; > > if (type != MXC_CPU_MX6SL) { > reg = readl(&anatop->digprog); > @@ -79,8 +80,9 @@ u32 get_cpu_rev(void) > } > > } > + major = ((reg >> 8) & 0xff); > reg &= 0xff; /* mx6 silicon revision */ > - return (type << 12) | (reg + 0x10); > + return (type << 12) | (reg + (0x10 * (major + 1))); > } > > /* > diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h > index 0d38d45..35a324c 100644 > --- a/arch/arm/include/asm/arch-mx6/imx-regs.h > +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h > @@ -312,6 +312,7 @@ > #define CHIP_REV_1_0 0x10 > #define CHIP_REV_1_2 0x12 > #define CHIP_REV_1_5 0x15 > +#define CHIP_REV_2_0 0x20 > #ifndef CONFIG_MX6SX > #define IRAM_SIZE 0x00040000 > #else > diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h > index 9c827c9..c1d9c6d 100644 > --- a/arch/arm/include/asm/arch-mx6/sys_proto.h > +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h > @@ -2,6 +2,8 @@ > * (C) Copyright 2009 > * Stefano Babic, DENX Software Engineering, sbabic@denx.de. > * > + * (C) Copyright 2009-2015 Freescale Semiconductor, Inc. > + * > * SPDX-License-Identifier: GPL-2.0+ > */ > mmhhh..we have already discussed this topic, Copyright should not be changed by small changes in a file. > @@ -30,6 +32,10 @@ const char *get_imx_type(u32 imxtype); > unsigned imx_ddr_size(void); > void set_chipselect_size(int const); > > +#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \ > + is_cpu_type(MXC_CPU_MX6D)) && \ > + (is_soc_rev(CHIP_REV_2_0) >= 0)) > + As "insider" you could better explain me: it looks like there will be not a Quad/Dual with an increased chip revision. The new chip revision for i.MX6 is really the QP (P=perfect, as I see some workaround can be removed !) Is it correct ? Else this conflicts if a 6Q with a revision > 2 will be released. Best regards, Stefano Babic
Hi Stefano, On Wed, Jun 10, 2015 at 11:19:07AM +0200, Stefano Babic wrote: >Hi Peng, > >On 10/06/2015 10:06, Peng Fan wrote: >> Add new cpu type for i.MX6DQP and providing a dynamical >> detecting function. >> >> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> >> Signed-off-by: Ye.Li <B37916@freescale.com> >> --- >> arch/arm/cpu/armv7/mx6/soc.c | 4 +++- >> arch/arm/include/asm/arch-mx6/imx-regs.h | 1 + >> arch/arm/include/asm/arch-mx6/sys_proto.h | 6 ++++++ >> 3 files changed, 10 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c >> index b21bd03..29de624 100644 >> --- a/arch/arm/cpu/armv7/mx6/soc.c >> +++ b/arch/arm/cpu/armv7/mx6/soc.c >> @@ -62,6 +62,7 @@ u32 get_cpu_rev(void) >> struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; >> u32 reg = readl(&anatop->digprog_sololite); >> u32 type = ((reg >> 16) & 0xff); >> + u32 major; >> >> if (type != MXC_CPU_MX6SL) { >> reg = readl(&anatop->digprog); >> @@ -79,8 +80,9 @@ u32 get_cpu_rev(void) >> } >> >> } >> + major = ((reg >> 8) & 0xff); >> reg &= 0xff; /* mx6 silicon revision */ >> - return (type << 12) | (reg + 0x10); >> + return (type << 12) | (reg + (0x10 * (major + 1))); >> } >> >> /* >> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h >> index 0d38d45..35a324c 100644 >> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h >> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h >> @@ -312,6 +312,7 @@ >> #define CHIP_REV_1_0 0x10 >> #define CHIP_REV_1_2 0x12 >> #define CHIP_REV_1_5 0x15 >> +#define CHIP_REV_2_0 0x20 >> #ifndef CONFIG_MX6SX >> #define IRAM_SIZE 0x00040000 >> #else >> diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h >> index 9c827c9..c1d9c6d 100644 >> --- a/arch/arm/include/asm/arch-mx6/sys_proto.h >> +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h >> @@ -2,6 +2,8 @@ >> * (C) Copyright 2009 >> * Stefano Babic, DENX Software Engineering, sbabic@denx.de. >> * >> + * (C) Copyright 2009-2015 Freescale Semiconductor, Inc. >> + * >> * SPDX-License-Identifier: GPL-2.0+ >> */ >> > >mmhhh..we have already discussed this topic, Copyright should not be >changed by small changes in a file. oh. I missed to remove this. Thanks for correcting me. > >> @@ -30,6 +32,10 @@ const char *get_imx_type(u32 imxtype); >> unsigned imx_ddr_size(void); >> void set_chipselect_size(int const); >> >> +#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \ >> + is_cpu_type(MXC_CPU_MX6D)) && \ >> + (is_soc_rev(CHIP_REV_2_0) >= 0)) >> + > >As "insider" you could better explain me: it looks like there will be >not a Quad/Dual with an increased chip revision. The new chip revision >for i.MX6 is really the QP (P=perfect, as I see some workaround can be >removed !) > >Is it correct ? Else this conflicts if a 6Q with a revision > 2 will be >released. P mean plus. It is from 6Q, since ic did not give new chip id for id, we use revision. > >Best regards, >Stefano Babic > Regards, Peng. >-- >===================================================================== >DENX Software Engineering GmbH, Managing Director: Wolfgang Denk >HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany >Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de >=====================================================================
Hi Peng, On 10/06/2015 12:01, Peng Fan wrote: >>> +#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \ >>> + is_cpu_type(MXC_CPU_MX6D)) && \ >>> + (is_soc_rev(CHIP_REV_2_0) >= 0)) >>> + >> >> As "insider" you could better explain me: it looks like there will be >> not a Quad/Dual with an increased chip revision. The new chip revision >> for i.MX6 is really the QP (P=perfect, as I see some workaround can be >> removed !) >> >> Is it correct ? Else this conflicts if a 6Q with a revision > 2 will be >> released. > P mean plus. I know, it was only a joke ;-). There is not "perfect" SOC. > It is from 6Q, since ic did not give new chip id for id, we use > revision. This is ok now until a 6Q with revision 2 or greater will be released. Then there is a conflict and u-boot cannot identify a 6QP from a 6Q. But it is still ok if Freescale will *never* plan to release a newer 6Q. Is it ? Best regards, Stefano Babic
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index b21bd03..29de624 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -62,6 +62,7 @@ u32 get_cpu_rev(void) struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; u32 reg = readl(&anatop->digprog_sololite); u32 type = ((reg >> 16) & 0xff); + u32 major; if (type != MXC_CPU_MX6SL) { reg = readl(&anatop->digprog); @@ -79,8 +80,9 @@ u32 get_cpu_rev(void) } } + major = ((reg >> 8) & 0xff); reg &= 0xff; /* mx6 silicon revision */ - return (type << 12) | (reg + 0x10); + return (type << 12) | (reg + (0x10 * (major + 1))); } /* diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 0d38d45..35a324c 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -312,6 +312,7 @@ #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_2 0x12 #define CHIP_REV_1_5 0x15 +#define CHIP_REV_2_0 0x20 #ifndef CONFIG_MX6SX #define IRAM_SIZE 0x00040000 #else diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 9c827c9..c1d9c6d 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -2,6 +2,8 @@ * (C) Copyright 2009 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. * + * (C) Copyright 2009-2015 Freescale Semiconductor, Inc. + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -30,6 +32,10 @@ const char *get_imx_type(u32 imxtype); unsigned imx_ddr_size(void); void set_chipselect_size(int const); +#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \ + is_cpu_type(MXC_CPU_MX6D)) && \ + (is_soc_rev(CHIP_REV_2_0) >= 0)) + /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init()