diff mbox

[v4,1/3] target-mips: Misaligned memory accesses for R6

Message ID 1432134765-7680-2-git-send-email-yongbok.kim@imgtec.com
State New
Headers show

Commit Message

Yongbok Kim May 20, 2015, 3:12 p.m. UTC 
Release 6 requires misaligned memory access support for all ordinary memory
access instructions (for example, LW/SW, LWC1/SWC1).
However misaligned support is not provided for certain special memory accesses
such as atomics (for example, LL/SC).

Allows misaligned accesses from mips_cpu_do_unaligned_access() callback,
if it is a R6 core. As the helper functions of LL/SC is checking misalignment,
just allowing all for R6 is good enough.

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
---
 target-mips/op_helper.c      |    7 +++++++
 target-mips/translate_init.c |    2 +-
 2 files changed, 8 insertions(+), 1 deletions(-)

Comments

Richard Henderson May 20, 2015, 5:09 p.m. UTC | #1 
On 05/20/2015 08:12 AM, Yongbok Kim wrote:
> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
> index 73a8e45..58f02cf 100644
> --- a/target-mips/op_helper.c
> +++ b/target-mips/op_helper.c
> @@ -2215,6 +2215,13 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>      int error_code = 0;
>      int excp;
>  
> +    if (env->insn_flags & ISA_MIPS32R6) {
> +        /* Release 6 provides support for misaligned memory access for
> +         * all ordinary memory reference instructions
> +         * */
> +        return;
> +    }

This should be done instead with MO_UNALN, at translate time.
See target-ppc, DisasContext, default_tcg_memop_mask.


r~
Yongbok Kim May 21, 2015, 9:47 a.m. UTC | #2 
On 20/05/2015 18:09, Richard Henderson wrote:
> On 05/20/2015 08:12 AM, Yongbok Kim wrote:
>> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
>> index 73a8e45..58f02cf 100644
>> --- a/target-mips/op_helper.c
>> +++ b/target-mips/op_helper.c
>> @@ -2215,6 +2215,13 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>>      int error_code = 0;
>>      int excp;
>>  
>> +    if (env->insn_flags & ISA_MIPS32R6) {
>> +        /* Release 6 provides support for misaligned memory access for
>> +         * all ordinary memory reference instructions
>> +         * */
>> +        return;
>> +    }
> 
> This should be done instead with MO_UNALN, at translate time.
> See target-ppc, DisasContext, default_tcg_memop_mask.
> 
> 
> r~
> 

Fair enough. Actually I considered to pass the information but didn't
bother as this way is so simple.

Regards,
Yongbok
Richard Henderson May 21, 2015, 4:15 p.m. UTC | #3 
On 05/21/2015 02:47 AM, Yongbok Kim wrote:
> Fair enough. Actually I considered to pass the information but didn't
> bother as this way is so simple.

If you ever quit relying on a separate heck for atomics,
which you probably should, this would be incorrect.


r~
diff mbox

Patch

diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 73a8e45..58f02cf 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2215,6 +2215,13 @@  void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
     int error_code = 0;
     int excp;
 
+    if (env->insn_flags & ISA_MIPS32R6) {
+        /* Release 6 provides support for misaligned memory access for
+         * all ordinary memory reference instructions
+         * */
+        return;
+    }
+
     env->CP0_BadVAddr = addr;
 
     if (access_type == MMU_DATA_STORE) {
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 85a65e7..ec54fef 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -607,7 +607,7 @@  static const mips_def_t mips_defs[] =
     },
     {
         /* A generic CPU supporting MIPS64 Release 6 ISA.
-           FIXME: Support IEEE 754-2008 FP and misaligned memory accesses.
+           FIXME: Support IEEE 754-2008 FP.
                   Eventually this should be replaced by a real CPU model. */
         .name = "MIPS64R6-generic",
         .CP0_PRid = 0x00010000,