From patchwork Wed May 20 15:12:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Yongbok Kim X-Patchwork-Id: 474518 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0B2501402AE for ; Thu, 21 May 2015 01:16:34 +1000 (AEST) Received: from localhost ([::1]:52682 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yv5jT-0003AX-T9 for incoming@patchwork.ozlabs.org; Wed, 20 May 2015 11:16:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45731) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yv5ig-00021h-I1 for qemu-devel@nongnu.org; Wed, 20 May 2015 11:15:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yv5ib-00018W-4e for qemu-devel@nongnu.org; Wed, 20 May 2015 11:15:42 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:34846) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yv5ia-00018L-MJ for qemu-devel@nongnu.org; Wed, 20 May 2015 11:15:37 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 97CDB269D8E08; Wed, 20 May 2015 16:15:32 +0100 (IST) Received: from hhmail02.hh.imgtec.org (10.100.10.20) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 20 May 2015 16:14:31 +0100 Received: from localhost.localdomain (192.168.14.192) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.224.2; Wed, 20 May 2015 16:14:31 +0100 From: Yongbok Kim To: Date: Wed, 20 May 2015 16:12:43 +0100 Message-ID: <1432134765-7680-2-git-send-email-yongbok.kim@imgtec.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1432134765-7680-1-git-send-email-yongbok.kim@imgtec.com> References: <1432134765-7680-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.192] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: peter.maydell@linaro.org, leon.alrae@imgtec.com, afaerber@suse.de, rth@twiddle.net Subject: [Qemu-devel] [PATCH v4 1/3] target-mips: Misaligned memory accesses for R6 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Release 6 requires misaligned memory access support for all ordinary memory access instructions (for example, LW/SW, LWC1/SWC1). However misaligned support is not provided for certain special memory accesses such as atomics (for example, LL/SC). Allows misaligned accesses from mips_cpu_do_unaligned_access() callback, if it is a R6 core. As the helper functions of LL/SC is checking misalignment, just allowing all for R6 is good enough. Signed-off-by: Yongbok Kim Reviewed-by: Andreas Färber --- target-mips/op_helper.c | 7 +++++++ target-mips/translate_init.c | 2 +- 2 files changed, 8 insertions(+), 1 deletions(-) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 73a8e45..58f02cf 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -2215,6 +2215,13 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr, int error_code = 0; int excp; + if (env->insn_flags & ISA_MIPS32R6) { + /* Release 6 provides support for misaligned memory access for + * all ordinary memory reference instructions + * */ + return; + } + env->CP0_BadVAddr = addr; if (access_type == MMU_DATA_STORE) { diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 85a65e7..ec54fef 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -607,7 +607,7 @@ static const mips_def_t mips_defs[] = }, { /* A generic CPU supporting MIPS64 Release 6 ISA. - FIXME: Support IEEE 754-2008 FP and misaligned memory accesses. + FIXME: Support IEEE 754-2008 FP. Eventually this should be replaced by a real CPU model. */ .name = "MIPS64R6-generic", .CP0_PRid = 0x00010000,