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[U-Boot,v2,10/13] arm: mvebu: Add dynamic SoC detection to mbus driver

Message ID 1429008415-27458-11-git-send-email-sr@denx.de
State Superseded
Delegated to: Prafulla Wadaskar
Headers show

Commit Message

Stefan Roese April 14, 2015, 10:46 a.m. UTC 
This enables the mbus driver to also support other, newer Armada SoC
platforms. Like the newly added Armada 38x support.

Signed-off-by: Stefan Roese <sr@denx.de>
---

Changes in v2: None

 arch/arm/mach-mvebu/mbus.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

Comments

Thomas Petazzoni April 14, 2015, 3:31 p.m. UTC | #1 
Dear Stefan Roese,

On Tue, 14 Apr 2015 12:46:52 +0200, Stefan Roese wrote:

> +			if (mvebu_soc_family() == MVEBU_SOC_AXP)
> +				w->mbus_attr |= ATTR_HW_COHERENCY;

Why is this Armada XP specific? Both Armada XP and Armada 38x support
HW I/O coherency. But are you actually using HW I/O coherency in U-Boot
for Armada XP ?

It would probably be simpler to not use HW I/O coherency at all in
U-Boot, be it for AXP or A38x.

Best regards,

Thomas
Stefan Roese April 15, 2015, 8:45 a.m. UTC | #2 
Hi Thomas,

On 14.04.2015 17:31, Thomas Petazzoni wrote:
> On Tue, 14 Apr 2015 12:46:52 +0200, Stefan Roese wrote:
>
>> +			if (mvebu_soc_family() == MVEBU_SOC_AXP)
>> +				w->mbus_attr |= ATTR_HW_COHERENCY;
>
> Why is this Armada XP specific? Both Armada XP and Armada 38x support
> HW I/O coherency. But are you actually using HW I/O coherency in U-Boot
> for Armada XP ?

No, not really. This file is pretty much cloned from the Linux version. 
So its a remnant from there. Even though this coherency is not used in 
U-Boot.

> It would probably be simpler to not use HW I/O coherency at all in
> U-Boot, be it for AXP or A38x.

Right. I'll remove this, either in a new patchset version or in a follow 
up patch. Thanks for the hint.

Thanks,
Stefan
diff mbox

Patch

diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c
index 05c9ef2..72cbd21 100644
--- a/arch/arm/mach-mvebu/mbus.c
+++ b/arch/arm/mach-mvebu/mbus.c
@@ -341,9 +341,8 @@  static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
 			w = &mbus_dram_info.cs[cs++];
 			w->cs_index = i;
 			w->mbus_attr = 0xf & ~(1 << i);
-#if defined(CONFIG_ARMADA_XP)
-			w->mbus_attr |= ATTR_HW_COHERENCY;
-#endif
+			if (mvebu_soc_family() == MVEBU_SOC_AXP)
+				w->mbus_attr |= ATTR_HW_COHERENCY;
 			w->base = base & DDR_BASE_CS_LOW_MASK;
 			w->size = (size | ~DDR_SIZE_MASK) + 1;
 		}