diff mbox

[U-Boot] arm: ls102xa: workaround for cache coherency problem

Message ID 1421999633-20896-1-git-send-email-chenhui.zhao@freescale.com
State Accepted
Delegated to: York Sun
Headers show

Commit Message

chenhui zhao Jan. 23, 2015, 7:53 a.m. UTC 
The RCPM FSM may not be reset after power-on, for example,
in the cases of cold boot and wakeup from deep sleep.
It causes cache coherency problem and may block deep sleep.
Therefore, reset them if they are not be reset.

Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
---
 arch/arm/cpu/armv7/ls102xa/cpu.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

Comments

York Sun Feb. 25, 2015, 9:34 p.m. UTC | #1 
On 01/22/2015 11:53 PM, Chenhui Zhao wrote:
> The RCPM FSM may not be reset after power-on, for example,
> in the cases of cold boot and wakeup from deep sleep.
> It causes cache coherency problem and may block deep sleep.
> Therefore, reset them if they are not be reset.
> 
> Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
> ---

Applied to u-boot-fsl-qoriq master branch, awaiting upstream.

York
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index ce2d92f..a61f6d1 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -14,6 +14,13 @@ 
 
 #include "fsl_epu.h"
 
+#define DCSR_RCPM2_BLOCK_OFFSET	0x223000
+#define DCSR_RCPM2_CPMFSMCR0	0x400
+#define DCSR_RCPM2_CPMFSMSR0	0x404
+#define DCSR_RCPM2_CPMFSMCR1	0x414
+#define DCSR_RCPM2_CPMFSMSR1	0x418
+#define CPMFSMSR_FSM_STATE_MASK	0x7f
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
@@ -107,6 +114,27 @@  int cpu_eth_init(bd_t *bis)
 int arch_cpu_init(void)
 {
 	void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+	void *rcpm2_base =
+		(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+	u32 state;
+
+	/*
+	 * The RCPM FSM state may not be reset after power-on.
+	 * So, reset them.
+	 */
+	state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) &
+		CPMFSMSR_FSM_STATE_MASK;
+	if (state != 0) {
+		out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);
+		out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);
+	}
+
+	state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) &
+		CPMFSMSR_FSM_STATE_MASK;
+	if (state != 0) {
+		out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);
+		out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);
+	}
 
 	/*
 	 * After wakeup from deep sleep, Clear EPU registers