diff mbox

[U-Boot,v3,08/12] x86: dts: Add SPI flash MRC details for chromebook_link

Message ID 1421730977-30077-9-git-send-email-sjg@chromium.org
State Accepted
Delegated to: Simon Glass
Headers show

Commit Message

Simon Glass Jan. 20, 2015, 5:16 a.m. UTC
Correct the SPI flash compatible string, add an alias and specify the
position of the MRC cache, used to store SDRAM training settings for the
Memory Reference Code.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Drop accidental creation of link.dts due to bad rebase

Changes in v2:
- Make changes to chromebook_link.dts since link.dts is gone
- Use intel,ich-spi as the compatible string

 arch/x86/dts/chromebook_link.dts | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

Comments

Simon Glass Jan. 24, 2015, 1:31 p.m. UTC | #1
On 19 January 2015 at 22:16, Simon Glass <sjg@chromium.org> wrote:
> Correct the SPI flash compatible string, add an alias and specify the
> position of the MRC cache, used to store SDRAM training settings for the
> Memory Reference Code.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Drop accidental creation of link.dts due to bad rebase
>
> Changes in v2:
> - Make changes to chromebook_link.dts since link.dts is gone
> - Use intel,ich-spi as the compatible string
>
>  arch/x86/dts/chromebook_link.dts | 15 ++++++++++++++-
>  1 file changed, 14 insertions(+), 1 deletion(-)

Applied to u-boot-x86.
diff mbox

Patch

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 9490b16..45ada61 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -7,6 +7,10 @@ 
 	model = "Google Link";
 	compatible = "google,link", "intel,celeron-ivybridge";
 
+	aliases {
+		spi0 = "/spi";
+	};
+
 	config {
 	       silent_console = <0>;
 	};
@@ -150,11 +154,20 @@ 
 	spi {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		compatible = "intel,ich9";
+		compatible = "intel,ich-spi";
 		spi-flash@0 {
+			#size-cells = <1>;
+			#address-cells = <1>;
 			reg = <0>;
 			compatible = "winbond,w25q64", "spi-flash";
 			memory-map = <0xff800000 0x00800000>;
+			rw-mrc-cache {
+				label = "rw-mrc-cache";
+				/* Alignment: 4k (for updating) */
+				reg = <0x003e0000 0x00010000>;
+				type = "wiped";
+				wipe-value = [ff];
+			};
 		};
 	};