diff mbox

[U-Boot] ARM: UniPhier: enable output of system bus

Message ID 1420521604-13646-1-git-send-email-yamada.m@jp.panasonic.com
State Accepted
Delegated to: Masahiro Yamada
Headers show

Commit Message

Masahiro Yamada Jan. 6, 2015, 5:20 a.m. UTC
For NAND boot on PH1-LD4, PH1-sLD8, and some other SoCs,
the output of the system bus is disabled by default.
It must be enabled by software to have access to the system bus.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
---

 arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c  | 7 +++++++
 arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c | 7 +++++++
 arch/arm/include/asm/arch-uniphier/sbc-regs.h   | 1 +
 3 files changed, 15 insertions(+)

Comments

Masahiro Yamada Jan. 8, 2015, 2:05 p.m. UTC | #1
2015-01-06 14:20 GMT+09:00 Masahiro Yamada <yamada.m@jp.panasonic.com>:
> For NAND boot on PH1-LD4, PH1-sLD8, and some other SoCs,
> the output of the system bus is disabled by default.
> It must be enabled by software to have access to the system bus.
>
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>


Applied to u-boot-uniphier/master
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
index a37ed16..4839c94 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
@@ -12,6 +12,13 @@ 
 
 void sbc_init(void)
 {
+	u32 tmp;
+
+	/* system bus output enable */
+	tmp = readl(PC0CTRL);
+	tmp &= 0xfffffcff;
+	writel(tmp, PC0CTRL);
+
 	/* XECS1: sub/boot memory (boot swap = off/on) */
 	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
 	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
index af44dee..5efee9c 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
@@ -12,6 +12,13 @@ 
 
 void sbc_init(void)
 {
+	u32 tmp;
+
+	/* system bus output enable */
+	tmp = readl(PC0CTRL);
+	tmp &= 0xfffffcff;
+	writel(tmp, PC0CTRL);
+
 #if !defined(CONFIG_SPL_BUILD)
 	/* XECS0 : dummy */
 	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
diff --git a/arch/arm/include/asm/arch-uniphier/sbc-regs.h b/arch/arm/include/asm/arch-uniphier/sbc-regs.h
index 8e41078..efb68e8 100644
--- a/arch/arm/include/asm/arch-uniphier/sbc-regs.h
+++ b/arch/arm/include/asm/arch-uniphier/sbc-regs.h
@@ -95,6 +95,7 @@ 
 #define SBCTRL1_ADMULTIPLX_MEM_VALUE	0x03005500
 #define SBCTRL2_ADMULTIPLX_MEM_VALUE	0x14000010
 
+#define PC0CTRL				0x598000c0
 #define ROM_BOOT_ROMRSV2		0x59801208
 
 #ifndef __ASSEMBLY__