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[v1,1/1] target-tricore: fix offset masking in BOL format + typo

Message ID 548AC2A4.6010009@hs-rm.de
State New
Headers show

Commit Message

Alex Zuepke Dec. 12, 2014, 10:25 a.m. UTC 
Fixes offset masking for BOL opcodes and a typo (LONF -> LONG)

Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de>
--

Comments

Bastian Koppelmann Dec. 12, 2014, 1:20 p.m. UTC | #1 
On 12/12/2014 10:25 AM, Alex Züpke wrote:
> Fixes offset masking for BOL opcodes and a typo (LONF -> LONG)
>
> Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de>
Hi Alex,

good catch. I wonder how that slipped through my testsuit. However you 
mail seems to be malformed. The patch went somehow into your signature. 
Don't do that, please. It is easier for the reviewer and you, if he can 
inline comments to the corresponding line, he wants to talk about. Also 
you don't need a v1 for the first version of a patch and please group up 
similar patches, e.g. for tricore.

The usual workflow with git would be, for your two patches:

1) git format-patch -2 --cover-letter
2) edit coverletter and say, what the patches are doing.
3) git send-email --to="qemu-devel@nongnu.org" --cc=... *.patch

Other than that, it looks good to me. If you resend your two patches 
well formated, I'll add them to my tricore-next branch.

Cheers,
Bastian
diff mbox

Patch

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 65abf45..c132223 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3203,7 +3203,7 @@  static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
         tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
         tcg_temp_free(temp);
         break;
-    case OPC1_32_BOL_LD_W_LONFOFF:
+    case OPC1_32_BOL_LD_W_LONGOFF:
         temp = tcg_temp_new();
         tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
         tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
@@ -3930,7 +3930,7 @@  static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
         break;
 /* BOL-format */
     case OPC1_32_BOL_LD_A_LONGOFF:
-    case OPC1_32_BOL_LD_W_LONFOFF:
+    case OPC1_32_BOL_LD_W_LONGOFF:
     case OPC1_32_BOL_LEA_LONGOFF:
     case OPC1_32_BOL_ST_W_LONGOFF:
     case OPC1_32_BOL_ST_A_LONGOFF:
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 0a9122c..7aa6aed 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -114,7 +114,7 @@ 
 /* BOL Format */
 #define MASK_OP_BOL_OFF16(op)  ((MASK_BITS_SHIFT(op, 16, 21) +        \
                                (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
-                               (MASK_BITS_SHIFT(op, 22, 27) >> 10))
+                               (MASK_BITS_SHIFT(op, 22, 27) << 10))
 #define MASK_OP_BOL_OFF16_SEXT(op)  ((MASK_BITS_SHIFT(op, 16, 21) +        \
                                     (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
                                     (MASK_BITS_SHIFT_SEXT(op, 22, 27) << 10))
@@ -447,7 +447,7 @@  enum {
     OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR    = 0x69,
 /* BOL Format */
     OPC1_32_BOL_LD_A_LONGOFF                         = 0x99,
-    OPC1_32_BOL_LD_W_LONFOFF                         = 0x19,
+    OPC1_32_BOL_LD_W_LONGOFF                         = 0x19,
     OPC1_32_BOL_LEA_LONGOFF                          = 0xd9,
     OPC1_32_BOL_ST_W_LONGOFF                         = 0x59,
     OPC1_32_BOL_ST_A_LONGOFF                         = 0xb5, /* 1.6 only */