From patchwork Fri Dec 12 10:25:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Zuepke X-Patchwork-Id: 420425 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 02335140081 for ; Fri, 12 Dec 2014 21:26:21 +1100 (AEDT) Received: from localhost ([::1]:56397 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzNQQ-0002v3-S0 for incoming@patchwork.ozlabs.org; Fri, 12 Dec 2014 05:26:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41470) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzNQ5-0002eb-P9 for qemu-devel@nongnu.org; Fri, 12 Dec 2014 05:26:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XzNPz-0006BX-TC for qemu-devel@nongnu.org; Fri, 12 Dec 2014 05:25:57 -0500 Received: from mxout-1k.itc.hs-rm.de ([195.72.102.133]:50360) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzNPz-000699-KL for qemu-devel@nongnu.org; Fri, 12 Dec 2014 05:25:51 -0500 Received: from EXCHANGE-3K.hds.local ([10.10.35.1]) by mxout-1k.itc.hs-rm.de (8.14.4/8.14.4) with ESMTP id sBCAPexT009990; Fri, 12 Dec 2014 11:25:41 +0100 (envelope-from Alexander.Zuepke@hs-rm.de) Received: from [195.72.96.249] (10.151.1.3) by EXCHANGE-3K.hds.local (10.10.62.124) with Microsoft SMTP Server (TLS) id 14.3.195.1; Fri, 12 Dec 2014 11:25:40 +0100 Message-ID: <548AC2A4.6010009@hs-rm.de> Date: Fri, 12 Dec 2014 11:25:40 +0100 From: =?UTF-8?B?QWxleCBaw7xwa2U=?= User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 MIME-Version: 1.0 To: X-Originating-IP: [10.151.1.3] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 195.72.102.133 Cc: Bastian Koppelmann Subject: [Qemu-devel] [PATCH v1 1/1] target-tricore: fix offset masking in BOL format + typo X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Fixes offset masking for BOL opcodes and a typo (LONF -> LONG) Signed-off-by: Alex Zuepke diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 65abf45..c132223 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -3203,7 +3203,7 @@ static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1) tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL); tcg_temp_free(temp); break; - case OPC1_32_BOL_LD_W_LONFOFF: + case OPC1_32_BOL_LD_W_LONGOFF: temp = tcg_temp_new(); tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL); @@ -3930,7 +3930,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) break; /* BOL-format */ case OPC1_32_BOL_LD_A_LONGOFF: - case OPC1_32_BOL_LD_W_LONFOFF: + case OPC1_32_BOL_LD_W_LONGOFF: case OPC1_32_BOL_LEA_LONGOFF: case OPC1_32_BOL_ST_W_LONGOFF: case OPC1_32_BOL_ST_A_LONGOFF: diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index 0a9122c..7aa6aed 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -114,7 +114,7 @@ /* BOL Format */ #define MASK_OP_BOL_OFF16(op) ((MASK_BITS_SHIFT(op, 16, 21) + \ (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \ - (MASK_BITS_SHIFT(op, 22, 27) >> 10)) + (MASK_BITS_SHIFT(op, 22, 27) << 10)) #define MASK_OP_BOL_OFF16_SEXT(op) ((MASK_BITS_SHIFT(op, 16, 21) + \ (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \ (MASK_BITS_SHIFT_SEXT(op, 22, 27) << 10)) @@ -447,7 +447,7 @@ enum { OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR = 0x69, /* BOL Format */ OPC1_32_BOL_LD_A_LONGOFF = 0x99, - OPC1_32_BOL_LD_W_LONFOFF = 0x19, + OPC1_32_BOL_LD_W_LONGOFF = 0x19, OPC1_32_BOL_LEA_LONGOFF = 0xd9, OPC1_32_BOL_ST_W_LONGOFF = 0x59, OPC1_32_BOL_ST_A_LONGOFF = 0xb5, /* 1.6 only */