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[1/1] arm_gic: gic_update should always update all cores.

Message ID 5006DF1F5103294E8DA02CC4C71B1BF8085C0F1C@SESTOEX04.enea.se
State New
Headers show

Commit Message

Johan Karlsson Nov. 13, 2014, 5:08 p.m. UTC 
This patch fixes so that gic_update always updates all the cores with new pending irq states.
If the function returns early it is possible to get interrupts that has already been acknowledged.

Signed-off-by: Johan Karlsson <johan.karlsson@enea.com>

Comments

Peter Maydell June 5, 2015, 12:48 p.m. UTC | #1 
On 13 November 2014 at 17:08, Johan Karlsson <Johan.Karlsson@enea.com> wrote:
> This patch fixes so that gic_update always updates all the cores with new pending irq states.
> If the function returns early it is possible to get interrupts that has already been acknowledged.
>
> Signed-off-by: Johan Karlsson <johan.karlsson@enea.com>
>
> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
> index 270ce05..f1641f5 100644
> --- a/hw/intc/arm_gic.c
> +++ b/hw/intc/arm_gic.c
> @@ -61,7 +61,7 @@ void gic_update(GICState *s)
>          s->current_pending[cpu] = 1023;
>          if (!s->enabled || !s->cpu_enabled[cpu]) {
>              qemu_irq_lower(s->parent_irq[cpu]);
> -            return;
> +            continue;
>          }
>          best_prio = 0x100;
>          best_irq = 1023;

Oops, this dropped through the cracks of the review process, but
Johan just pinged me on IRC about it.

Applied to target-arm.next, thanks.

-- PMM
diff mbox

Patch

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 270ce05..f1641f5 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -61,7 +61,7 @@  void gic_update(GICState *s)
         s->current_pending[cpu] = 1023;
         if (!s->enabled || !s->cpu_enabled[cpu]) {
             qemu_irq_lower(s->parent_irq[cpu]);
-            return;
+            continue;
         }
         best_prio = 0x100;
         best_irq = 1023;