diff mbox

[U-Boot,1/3] 85xx/b4860: Add alternate serdes protocols for B4860/B4420

Message ID 1415788345-28843-1-git-send-email-shaveta@freescale.com
State Accepted
Delegated to: York Sun
Headers show

Commit Message

Shaveta Leekha Nov. 12, 2014, 10:32 a.m. UTC 
Addded Alternate options with LC VCO for following protocols:
0x02 --> 0x01
0x08 --> 0x07
0x18 --> 0x17
0x1E --> 0x1D
0x49 --> 0x48
0x6F --> 0x6E
0x9A --> 0x99
0x9E --> 0x9D

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Change-Id: Iefe14012ee897095f0198453d50f31096ca020e2
Reviewed-on: http://git.am.freescale.net:8181/23352
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yusong Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/b4860_serdes.c |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+), 0 deletions(-)

Comments

York Sun Nov. 17, 2014, 5:02 p.m. UTC | #1 
On 11/12/2014 02:32 AM, Shaveta Leekha wrote:
> Addded Alternate options with LC VCO for following protocols:
> 0x02 --> 0x01
> 0x08 --> 0x07
> 0x18 --> 0x17
> 0x1E --> 0x1D
> 0x49 --> 0x48
> 0x6F --> 0x6E
> 0x9A --> 0x99
> 0x9E --> 0x9D
> 
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> Change-Id: Iefe14012ee897095f0198453d50f31096ca020e2
> Reviewed-on: http://git.am.freescale.net:8181/23352
> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
> Reviewed-by: Yusong Sun <yorksun@freescale.com>
> ---

First, you should remove internal review information when you send patches to
this mailing list. Please do so from for your next patch.

Second, when you resend or update the patches, please add a change log and
update the version number.

York
York Sun Dec. 5, 2014, 4:34 p.m. UTC | #2 
On 11/12/2014 02:32 AM, Shaveta Leekha wrote:
> Addded Alternate options with LC VCO for following protocols:
> 0x02 --> 0x01
> 0x08 --> 0x07
> 0x18 --> 0x17
> 0x1E --> 0x1D
> 0x49 --> 0x48
> 0x6F --> 0x6E
> 0x9A --> 0x99
> 0x9E --> 0x9D
> 
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> Change-Id: Iefe14012ee897095f0198453d50f31096ca020e2
> Reviewed-on: http://git.am.freescale.net:8181/23352
> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
> Reviewed-by: Yusong Sun <yorksun@freescale.com>
> ---

Applied to u-boot-mpc85xx, awaiting upstream.

York
diff mbox

Patch

diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
index cf18be5..63172de 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
@@ -18,6 +18,8 @@  struct serdes_config {
 #ifdef CONFIG_PPC_B4860
 static struct serdes_config serdes1_cfg_tbl[] = {
 	/* SerDes 1 */
+	{0x01, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x02, {AURORA, AURORA, CPRI6, CPRI5,
 		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x04, {AURORA, AURORA, CPRI6, CPRI5,
@@ -26,6 +28,8 @@  static struct serdes_config serdes1_cfg_tbl[] = {
 		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x06, {AURORA, AURORA, CPRI6, CPRI5,
 		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x07, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x08, {AURORA, AURORA, CPRI6, CPRI5,
 		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x09, {AURORA, AURORA, CPRI6, CPRI5,
@@ -184,12 +188,17 @@  static struct serdes_config serdes1_cfg_tbl[] = {
 		CPRI4, CPRI3, NONE, NONE} },
 	{0x0F, {NONE, NONE, CPRI6, CPRI5,
 		CPRI4, CPRI3, NONE, NONE} },
+	{0x17, {NONE, NONE,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		NONE, NONE, NONE, NONE} },
 	{0x18, {NONE, NONE,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		NONE, NONE, NONE, NONE} },
 	{0x1B, {NONE, NONE,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		NONE, NONE, NONE, NONE} },
+	{0x1D, {NONE, NONE, AURORA, AURORA,
+		NONE, NONE, NONE, NONE} },
 	{0x1E, {NONE, NONE, AURORA, AURORA,
 		NONE, NONE, NONE, NONE} },
 	{0x21, {NONE, NONE, AURORA, AURORA,
@@ -199,19 +208,29 @@  static struct serdes_config serdes1_cfg_tbl[] = {
 	{}
 };
 static struct serdes_config serdes2_cfg_tbl[] = {
+	{0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, AURORA,
+		NONE, NONE, NONE, NONE} },
 	{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, AURORA,
 		NONE, NONE, NONE, NONE} },
 	{0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, AURORA,
 		NONE, NONE, NONE, NONE} },
+	{0x6E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		AURORA, AURORA, NONE, NONE, NONE, NONE} },
 	{0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		AURORA, AURORA,	NONE, NONE, NONE, NONE} },
 	{0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		AURORA, AURORA,	NONE, NONE, NONE, NONE} },
+	{0x99, {PCIE1, PCIE1,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		NONE, NONE, NONE, NONE} },
 	{0x9A, {PCIE1, PCIE1,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		NONE, NONE, NONE, NONE} },
+	{0x9D, {PCIE1, PCIE1, PCIE1, PCIE1,
+		NONE, NONE, NONE, NONE} },
 	{0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
 		NONE, NONE, NONE, NONE} },
 	{}